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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28dd83sm95189866b.25.2024.11.22.04.27.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Nov 2024 04:27:03 -0800 (PST) Message-ID: Date: Fri, 22 Nov 2024 13:27:00 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node To: Yijie Yang , Andrew Lunn Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org References: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> <20241118-dts_qcs615-v2-2-e62b924a3cbd@quicinc.com> <89a4f120-6cfd-416d-ab55-f0bdf069d9ce@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <89a4f120-6cfd-416d-ab55-f0bdf069d9ce@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: SM-yLl1ZoPKEKeYpjx_UEXq3rdljQjMB X-Proofpoint-GUID: SM-yLl1ZoPKEKeYpjx_UEXq3rdljQjMB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 mlxscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=829 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220106 On 19.11.2024 11:09 AM, Yijie Yang wrote: > > > On 2024-11-19 09:27, Andrew Lunn wrote: >> On Mon, Nov 18, 2024 at 02:44:02PM +0800, Yijie Yang wrote: >>> Enable the ethernet node, add the phy node and pinctrl for ethernet. >>> >>> Signed-off-by: Yijie Yang >>> --- >>>   arch/arm64/boot/dts/qcom/qcs615-ride.dts | 106 +++++++++++++++++++++++++++++++ >>>   1 file changed, 106 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>> index ee6cab3924a6d71f29934a8debba3a832882abdd..299be3aa17a0633d808f4b5d32aed946f07d5dfd 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts >>> @@ -5,6 +5,7 @@ >>>   /dts-v1/; >>>     #include >>> +#include >>>   #include "qcs615.dtsi" >>>   / { >>>       model = "Qualcomm Technologies, Inc. QCS615 Ride"; >>> @@ -196,6 +197,60 @@ vreg_l17a: ldo17 { >>>       }; >>>   }; >>>   +ðernet { >>> +    status = "okay"; >>> + >>> +    pinctrl-0 = <ðernet_defaults>; >>> +    pinctrl-names = "default"; >>> + >>> +    phy-handle = <&rgmii_phy>; >>> +    phy-mode = "rgmii"; >> >> That is unusual. Does the board have extra long clock lines? > > Do you mean to imply that using RGMII mode is unusual? While the EMAC controller supports various modes, due to hardware design limitations, only RGMII mode can be effectively implemented. Is that a board-specific issue, or something that concerns the SoC itself? > >> >>> +    max-speed = <1000>; >> >> Why do you have this property? It is normally used to slow the MAC >> down because of issues at higher speeds. > > According to the databoot, the EMAC in RGMII mode can support speeds of up to 1Gbps. I believe the question Andrew is asking is "how is that effectively different from the default setting (omitting the property)?" Konrad