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Sun, 10 May 2026 23:34:54 -0700 (PDT) X-Received: by 2002:a17:90b:2884:b0:366:159a:c1ba with SMTP id 98e67ed59e1d1-3664c8db9acmr14006506a91.3.1778481294151; Sun, 10 May 2026 23:34:54 -0700 (PDT) Received: from [10.206.105.200] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1ebe0e8sm97390245ad.76.2026.05.10.23.34.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 May 2026 23:34:53 -0700 (PDT) Message-ID: Date: Mon, 11 May 2026 12:04:47 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH 09/16] media: iris: Add framework support for AR50_LITE video core Content-Language: en-US To: Dmitry Baryshkov , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Dikshita Agarwal References: <20260507-iris-ar50lt-v1-0-d22cccedc3e2@oss.qualcomm.com> <20260507-iris-ar50lt-v1-9-d22cccedc3e2@oss.qualcomm.com> From: Vishnu Reddy In-Reply-To: <20260507-iris-ar50lt-v1-9-d22cccedc3e2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: YQTE-EjDSzvStzcnMtGLaK6vGqcWST3f X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTExMDA3MCBTYWx0ZWRfX77Qa1BcztxVT 7sScp3UwHfty3qbCAwqD426kVlIEhNXySsvGFkeAWNJvMmYV6wPaPAJrcBvl3ZXg9q/cnKMmFXA qp+Pnp+WiC6ffQCo+exCS49eZ3gDoOyzgQGLOhBU97KJtFNwuDLgy90AtQzm4HfQTux+uKxtUIo 7ammZFOIUi+87+DHB22Lg3lYX5ZxJ1WT7pad/T9d5A0YeiyqVnaIJUGR4aX+2YII58QzmakAT2x tpZSNmqpIwjaWSDeNuUJsTEYIjcPjrRSKStQbp3XOxgRc7SQkemKMfdq9wagmiPFTr/Vcuo4iiN dC5tdKwfN8N0V0fueU51b41DrKPq24xvUntLJxvODHPK8tig1U2CKHeHLA9nBMjyOZR9GW2Djpd Pu46Bh2ZAbbOfR+oQGkfOdbuhG9EOSNts8fuUXAohPTCqsH/DB+uH0GYU8zT5KGtb/avLmB+vj+ Ptxf4xW0pcq373un2ow== X-Proofpoint-GUID: YQTE-EjDSzvStzcnMtGLaK6vGqcWST3f X-Authority-Analysis: v=2.4 cv=Yvo/gYYX c=1 sm=1 tr=0 ts=6a01788f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=USSJgBeZPGwVCPz7ayEA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 impostorscore=0 spamscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605110070 On 5/7/2026 12:12 PM, Dmitry Baryshkov wrote: > From: Dikshita Agarwal > > Add power sequence for ar5lt core. > Add register handling for ar50lt by hooking up vpu op with ar50lt > specific implemtation or resue from earlier generation wherever > feasible. > > Signed-off-by: Dikshita Agarwal > Signed-off-by: Dmitry Baryshkov > --- > drivers/media/platform/qcom/iris/Makefile | 1 + > .../platform/qcom/iris/iris_platform_common.h | 2 + > drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c | 156 +++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.c | 3 +- > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > 5 files changed, 162 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile > index 48e415cbc439..f1b204b95694 100644 > --- a/drivers/media/platform/qcom/iris/Makefile > +++ b/drivers/media/platform/qcom/iris/Makefile > @@ -26,6 +26,7 @@ qcom-iris-objs += iris_buffer.o \ > iris_vpu2.o \ > iris_vpu3x.o \ > iris_vpu4x.o \ > + iris_vpu_ar50lt.o \ > iris_vpu_buffer.o \ > iris_vpu_common.o \ > > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index e1dc226066c1..4a0895bf5720 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -63,6 +63,7 @@ enum platform_clk_type { > IRIS_VPP0_HW_CLK, > IRIS_VPP1_HW_CLK, > IRIS_APV_HW_CLK, > + IRIS_THROTTLE_CLK, > }; > > struct platform_clk_data { > @@ -283,6 +284,7 @@ struct iris_platform_data { > u32 tz_cp_config_data_size; > u32 num_vpp_pipe; > bool no_aon; > + bool no_rpmh; > u32 wd_intr_mask; > u32 icc_ib_multiplier; > u32 max_session_count; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c > new file mode 100644 > index 000000000000..688b57291a81 > --- /dev/null > +++ b/drivers/media/platform/qcom/iris/iris_vpu_ar50lt.c > @@ -0,0 +1,156 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > + > +#include "iris_instance.h" > +#include "iris_vpu_common.h" > + > +#include "iris_vpu_register_defines.h" > + > +#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT BIT(3) > + > +#define WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT 0xb0080 > + > +#define CPU_CS_VCICMD 0xa0020 > +#define CPU_CS_VCICMD_ARP_OFF 0x1 > + > +static void iris_vpu_ar50lt_set_preset_registers(struct iris_core *core) > +{ > + writel(0x0, core->reg_base + WRAPPER_VCODEC0_CLOCK_CONFIG_AR50LT); > +} > + > +static void iris_vpu_ar50lt_interrupt_init(struct iris_core *core) > +{ > + writel(WRAPPER_INTR_MASK_A2HVCODEC_BMSK_AR50LT, core->reg_base + WRAPPER_INTR_MASK); > +} > + > +static void iris_vpu_ar50lt_disable_arp(struct iris_core *core) > +{ > + writel(CPU_CS_VCICMD_ARP_OFF, core->reg_base + CPU_CS_VCICMD); > +} > + > +static int iris_vpu_ar50lt_power_off_controller(struct iris_core *core) > +{ > + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); > + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); > + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); > + > + return 0; > +} > + > +static void iris_vpu_ar50lt_power_off_hw(struct iris_core *core) > +{ > + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); > + iris_disable_unprepare_clock(core, IRIS_THROTTLE_CLK); > + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); > + iris_disable_unprepare_clock(core, IRIS_HW_CLK); > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > +} > + > +static int iris_vpu_ar50lt_power_on_controller(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); > + if (ret) > + return ret; > + > + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK); > + if (ret) > + goto err_disable_power; > + > + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); > + if (ret && ret != -ENOENT) > + goto err_disable_ctrl_clock; > + > + ret = iris_prepare_enable_clock(core, IRIS_AHB_CLK); > + if (ret) > + goto err_disable_axi_clock; > + > + return 0; > + > +err_disable_axi_clock: > + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); > +err_disable_ctrl_clock: > + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); > +err_disable_power: > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); > + > + return ret; > +} > + > +static int iris_vpu_ar50lt_power_on_hw(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + if (ret) > + return ret; > + > + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); > + if (ret) > + goto err_disable_power; > + > + ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); > + if (ret) > + goto err_disable_hw_clock; > + > + ret = iris_prepare_enable_clock(core, IRIS_THROTTLE_CLK); > + if (ret && ret != -ENOENT) > + goto err_disable_hw_ahb_clock; > + Why the additional ret != -ENOENT check here? This function is hooked via iris_vpu_ar50lt_ops and IRIS_THROTTLE_CLK is explicitly defined in the qcm2290_data clock table, making it a mandatory clock for this platform. Is there any other platform that uses this same vpu hook but does not have the throttle clock? > + return 0; > + > +err_disable_hw_ahb_clock: > + iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); > +err_disable_hw_clock: > + iris_disable_unprepare_clock(core, IRIS_HW_CLK); > +err_disable_power: > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + > + return ret; > +} > + > +static u64 iris_vpu_ar50lt_calc_freq(struct iris_inst *inst, size_t data_size) > +{ > + struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps; > + struct v4l2_format *inp_f = inst->fmt_src; > + u32 mbs_per_second, mbpf, height, width; > + unsigned long vpp_freq, vsp_freq; > + u32 fps = DEFAULT_FPS; > + > + width = max(inp_f->fmt.pix_mp.width, inst->crop.width); > + height = max(inp_f->fmt.pix_mp.height, inst->crop.height); > + > + mbpf = NUM_MBS_PER_FRAME(height, width); > + mbs_per_second = mbpf * fps; > + > + vpp_freq = mbs_per_second * caps->mb_cycles_vpp; > + > + /* 21 / 20 is overhead factor */ > + vpp_freq += vpp_freq / 20; > + vsp_freq = mbs_per_second * caps->mb_cycles_vsp; > + > + /* 10 / 7 is overhead factor */ > + vsp_freq += ((fps * data_size * 8) * 10) / 7; > + > + return max(vpp_freq, vsp_freq); > +} > + > +const struct vpu_ops iris_vpu_ar50lt_ops = { > + .power_off_hw = iris_vpu_ar50lt_power_off_hw, > + .power_on_hw = iris_vpu_ar50lt_power_on_hw, > + .power_off_controller = iris_vpu_ar50lt_power_off_controller, > + .power_on_controller = iris_vpu_ar50lt_power_on_controller, > + .calc_freq = iris_vpu_ar50lt_calc_freq, > + .set_hwmode = iris_vpu_set_hwmode, > + .set_preset_registers = iris_vpu_ar50lt_set_preset_registers, > + .interrupt_init = iris_vpu_ar50lt_interrupt_init, > + .disable_arp = iris_vpu_ar50lt_disable_arp, > +}; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c > index b8300195a43b..f3607c0ca847 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c > @@ -97,7 +97,8 @@ int iris_vpu_boot_firmware(struct iris_core *core) > } > > writel(HOST2XTENSA_INTR_ENABLE, core->reg_base + CPU_CS_H2XSOFTINTEN); > - writel(0x0, core->reg_base + CPU_CS_X2RPMH); > + if (!core->iris_platform_data->no_rpmh) > + writel(0x0, core->reg_base + CPU_CS_X2RPMH); > > return 0; > } > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h > index 71d96921ed37..f00e2de5fa53 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h > @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; > extern const struct vpu_ops iris_vpu33_ops; > extern const struct vpu_ops iris_vpu35_ops; > extern const struct vpu_ops iris_vpu4x_ops; > +extern const struct vpu_ops iris_vpu_ar50lt_ops; > > struct vpu_ops { > void (*power_off_hw)(struct iris_core *core); >