[RFC PATCH 04/10] thermal/drivers/tsens: drop single-cell code for mdm9607

Dmitry Baryshkov
2022-09-10T12:47:14Z

There is no dtsi file for mdm9607 in the kernel sources. Drop the
compatibility with unofficial dtsi and remove support for handling the
single-cell calibration data on mdm9607.

Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/thermal/qcom/tsens-v0_1.c | 84 +------------------------------
1 file changed, 1 insertion(+), 83 deletions(-)

diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c
index add5d9dbc9d4..c3613b7ccc19 100644
--- a/drivers/thermal/qcom/tsens-v0_1.c
+++ b/drivers/thermal/qcom/tsens-v0_1.c
@@ -133,39 +133,6 @@

#define BIT_APPEND 0x3

-/* eeprom layout data for mdm9607 */
-#define MDM9607_BASE0_MASK 0x000000ff
-#define MDM9607_BASE1_MASK 0x000ff000
-#define MDM9607_BASE0_SHIFT 0
-#define MDM9607_BASE1_SHIFT 12
-
-#define MDM9607_S0_P1_MASK 0x00003f00
-#define MDM9607_S1_P1_MASK 0x03f00000
-#define MDM9607_S2_P1_MASK 0x0000003f
-#define MDM9607_S3_P1_MASK 0x0003f000
-#define MDM9607_S4_P1_MASK 0x0000003f
-
-#define MDM9607_S0_P2_MASK 0x000fc000
-#define MDM9607_S1_P2_MASK 0xfc000000
-#define MDM9607_S2_P2_MASK 0x00000fc0
-#define MDM9607_S3_P2_MASK 0x00fc0000
-#define MDM9607_S4_P2_MASK 0x00000fc0
-
-#define MDM9607_S0_P1_SHIFT 8
-#define MDM9607_S1_P1_SHIFT 20
-#define MDM9607_S2_P1_SHIFT 0
-#define MDM9607_S3_P1_SHIFT 12
-#define MDM9607_S4_P1_SHIFT 0
-
-#define MDM9607_S0_P2_SHIFT 14
-#define MDM9607_S1_P2_SHIFT 26
-#define MDM9607_S2_P2_SHIFT 6
-#define MDM9607_S3_P2_SHIFT 18
-#define MDM9607_S4_P2_SHIFT 6
-
-#define MDM9607_CAL_SEL_MASK 0x00700000
-#define MDM9607_CAL_SEL_SHIFT 20
-
static int calibrate_8916(struct tsens_priv *priv)
{
int base0 = 0, base1 = 0, i;
@@ -370,56 +337,7 @@ static int calibrate_8974(struct tsens_priv *priv)

static int calibrate_9607(struct tsens_priv *priv)
{
- int base, i;
- u32 p1[5], p2[5];
- int mode = 0;
- u32 *qfprom_cdata;
- int ret;
-
- ret = tsens_calibrate_nvmem(priv, 2);
- if (!ret)
- return 0;
-
- qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
- if (IS_ERR(qfprom_cdata))
- return PTR_ERR(qfprom_cdata);
-
- mode = (qfprom_cdata[2] & MDM9607_CAL_SEL_MASK) >> MDM9607_CAL_SEL_SHIFT;
- dev_dbg(priv->dev, "calibration mode is %d\n", mode);
-
- switch (mode) {
- case TWO_PT_CALIB:
- base = (qfprom_cdata[2] & MDM9607_BASE1_MASK) >> MDM9607_BASE1_SHIFT;
- p2[0] = (qfprom_cdata[0] & MDM9607_S0_P2_MASK) >> MDM9607_S0_P2_SHIFT;
- p2[1] = (qfprom_cdata[0] & MDM9607_S1_P2_MASK) >> MDM9607_S1_P2_SHIFT;
- p2[2] = (qfprom_cdata[1] & MDM9607_S2_P2_MASK) >> MDM9607_S2_P2_SHIFT;
- p2[3] = (qfprom_cdata[1] & MDM9607_S3_P2_MASK) >> MDM9607_S3_P2_SHIFT;
- p2[4] = (qfprom_cdata[2] & MDM9607_S4_P2_MASK) >> MDM9607_S4_P2_SHIFT;
- for (i = 0; i < priv->num_sensors; i++)
- p2[i] = ((base + p2[i]) << 2);
- fallthrough;
- case ONE_PT_CALIB2:
- base = (qfprom_cdata[0] & MDM9607_BASE0_MASK);
- p1[0] = (qfprom_cdata[0] & MDM9607_S0_P1_MASK) >> MDM9607_S0_P1_SHIFT;
- p1[1] = (qfprom_cdata[0] & MDM9607_S1_P1_MASK) >> MDM9607_S1_P1_SHIFT;
- p1[2] = (qfprom_cdata[1] & MDM9607_S2_P1_MASK) >> MDM9607_S2_P1_SHIFT;
- p1[3] = (qfprom_cdata[1] & MDM9607_S3_P1_MASK) >> MDM9607_S3_P1_SHIFT;
- p1[4] = (qfprom_cdata[2] & MDM9607_S4_P1_MASK) >> MDM9607_S4_P1_SHIFT;
- for (i = 0; i < priv->num_sensors; i++)
- p1[i] = ((base + p1[i]) << 2);
- break;
- default:
- for (i = 0; i < priv->num_sensors; i++) {
- p1[i] = 500;
- p2[i] = 780;
- }
- break;
- }
-
- compute_intercept_slope(priv, p1, p2, mode);
- kfree(qfprom_cdata);
-
- return 0;
+ return tsens_calibrate_nvmem(priv, 2);
}

/* v0.1: 8916, 8939, 8974, 9607 */
--
2.35.1