[PATCH v2 0/2] Enable CTCU device for QCS8300

[PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
configurations as SA8775p platform.

Changes in V2:
1. Add Krzysztof's R-B tag for dt-binding patch.
2. Add Konrad's Acked-by tag for dt patch.
3. Rebased on tag next-20250623.
4. Missed email addresses for coresight's maintainers in V1, loop them.
Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/

Jie Gan (2):
  dt-bindings: arm: add CTCU device for QCS8300
  arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes

 .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
 arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
 2 files changed, 160 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] dt-bindings: arm: add CTCU device for QCS8300

[Jie Gan]

The CTCU device for QCS8300 shares the same configurations as SA8775p. Add
a fallback to enable the CTCU for QCS8300 to utilize the compitable of the
SA8775p.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
 .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml     | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index 843b52eaf872..7f3aa503da53 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -26,8 +26,13 @@ description: |
 
 properties:
   compatible:
-    enum:
-      - qcom,sa8775p-ctcu
+    oneOf:
+      - items:
+          - enum:
+              - qcom,qcs8300-ctcu
+          - const: qcom,sa8775p-ctcu
+      - enum:
+          - qcom,sa8775p-ctcu
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH v2 2/2] arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes

[Jie Gan]

Add CTCU and ETR nodes in DT to enable expected functionalities.

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/qcs8300.dtsi | 153 ++++++++++++++++++++++++++
 1 file changed, 153 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 7ada029c32c1..7c235dc7cbdd 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -2154,6 +2154,35 @@ lpass_ag_noc: interconnect@3c40000 {
 			qcom,bcm-voters = <&apps_bcm_voter>;
 		};
 
+		ctcu@4001000 {
+			compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu";
+			reg = <0x0 0x04001000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb";
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					ctcu_in0: endpoint {
+						remote-endpoint = <&etr0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					ctcu_in1: endpoint {
+						remote-endpoint = <&etr1_out>;
+					};
+				};
+			};
+		};
+
 		stm@4002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x04002000 0x0 0x1000>,
@@ -2348,6 +2377,122 @@ qdss_funnel_out: endpoint {
 			};
 		};
 
+		replicator@4046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x04046000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					qdss_rep_in: endpoint {
+						remote-endpoint = <&swao_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					qdss_rep_out0: endpoint {
+						remote-endpoint = <&etr_rep_in>;
+					};
+				};
+			};
+		};
+
+		tmc@4048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x04048000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			iommus = <&apps_smmu 0x04c0 0x00>;
+
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr0_in: endpoint {
+						remote-endpoint = <&etr_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etr0_out: endpoint {
+						remote-endpoint = <&ctcu_in0>;
+					};
+				};
+			};
+		};
+
+		replicator@404e000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0x0 0x0404e000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			in-ports {
+				port {
+					etr_rep_in: endpoint {
+						remote-endpoint = <&qdss_rep_out0>;
+					};
+				};
+			};
+
+			out-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					etr_rep_out0: endpoint {
+						remote-endpoint = <&etr0_in>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					etr_rep_out1: endpoint {
+						remote-endpoint = <&etr1_in>;
+					};
+				};
+			};
+		};
+
+		tmc@404f000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0x0 0x0404f000 0x0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			iommus = <&apps_smmu 0x04a0 0x40>;
+
+			arm,scatter-gather;
+			arm,buffer-size = <0x400000>;
+
+			in-ports {
+				port {
+					etr1_in: endpoint {
+						remote-endpoint = <&etr_rep_out1>;
+					};
+				};
+			};
+
+			out-ports {
+				port {
+					etr1_out: endpoint {
+						remote-endpoint = <&ctcu_in1>;
+					};
+				};
+			};
+		};
+
 		tpdm@4841000 {
 			compatible = "qcom,coresight-tpdm", "arm,primecell";
 			reg = <0x0 0x04841000 0x0 0x1000>;
@@ -2777,6 +2922,14 @@ out-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
+				port@0 {
+					reg = <0>;
+
+					swao_rep_out0: endpoint {
+						remote-endpoint = <&qdss_rep_in>;
+					};
+				};
+
 				port@1 {
 					reg = <1>;
 
-- 
2.34.1

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 6/24/2025 5:59 PM, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.

Hi dear maintainers,

I just realized it would be more efficient to introduce a common 
compatible string for SoCs that include two TMC ETR devices.

Most of these SoCs share the same CTCU data configuration, such as the 
offsets for the ATID and IRQ registers, because they integrate the same 
version of the CTCU hardware.

So I propose introducing a common compatible string, 
"coresight-ctcu-v2", to simplify the device tree configuration for these 
platforms.

Here is the new dt-binding format:

properties:
   compatible:
     oneOf:
       - items:
           - enum:
               - qcom,sa8775p-ctcu
               - qcom,qcs8300-ctcu
           - const: qcom,coresight-ctcu-v2
       - enum:
           - qcom,coresight-ctcu-v2

Thanks,
Jie

> 
> Changes in V2:
> 1. Add Krzysztof's R-B tag for dt-binding patch.
> 2. Add Konrad's Acked-by tag for dt patch.
> 3. Rebased on tag next-20250623.
> 4. Missed email addresses for coresight's maintainers in V1, loop them.
> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/
> 
> Jie Gan (2):
>    dt-bindings: arm: add CTCU device for QCS8300
>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
> 
>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>   2 files changed, 160 insertions(+), 2 deletions(-)
> 

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 6/25/2025 8:59 AM, Jie Gan wrote:
> 
> 
> On 6/24/2025 5:59 PM, Jie Gan wrote:
>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in 
>> binding to utilize
>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 
>> shares same
>> configurations as SA8775p platform.
> 
> Hi dear maintainers,
> 
> I just realized it would be more efficient to introduce a common 
> compatible string for SoCs that include two TMC ETR devices.
> 
> Most of these SoCs share the same CTCU data configuration, such as the 
> offsets for the ATID and IRQ registers, because they integrate the same 
> version of the CTCU hardware.
> 
> So I propose introducing a common compatible string, "coresight-ctcu- 
> v2", to simplify the device tree configuration for these platforms.
> 
> Here is the new dt-binding format:
> 
> properties:
>    compatible:
>      oneOf:
>        - items:
>            - enum:
>                - qcom,sa8775p-ctcu
>                - qcom,qcs8300-ctcu
>            - const: qcom,coresight-ctcu-v2
>        - enum:
>            - qcom,coresight-ctcu-v2
> 
> Thanks,
> Jie

Gentle ping.

Thanks,
Jie

> 
>>
>> Changes in V2:
>> 1. Add Krzysztof's R-B tag for dt-binding patch.
>> 2. Add Konrad's Acked-by tag for dt patch.
>> 3. Rebased on tag next-20250623.
>> 4. Missed email addresses for coresight's maintainers in V1, loop them.
>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- 
>> jie.gan@oss.qualcomm.com/
>>
>> Jie Gan (2):
>>    dt-bindings: arm: add CTCU device for QCS8300
>>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>
>>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>>   2 files changed, 160 insertions(+), 2 deletions(-)
>>
> 
> 

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Krzysztof Kozlowski]

On 25/06/2025 02:59, Jie Gan wrote:
> 
> 
> On 6/24/2025 5:59 PM, Jie Gan wrote:
>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
>> configurations as SA8775p platform.
> 
> Hi dear maintainers,
> 
> I just realized it would be more efficient to introduce a common 
> compatible string for SoCs that include two TMC ETR devices.
> 
> Most of these SoCs share the same CTCU data configuration, such as the 

"Most" basically disqualifies your idea.

> offsets for the ATID and IRQ registers, because they integrate the same 
> version of the CTCU hardware.
> 
> So I propose introducing a common compatible string, 
> "coresight-ctcu-v2", to simplify the device tree configuration for these 
> platforms.

This is explained in writing bindings.

Best regards,
Krzysztof

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 7/4/2025 3:54 PM, Krzysztof Kozlowski wrote:
> On 25/06/2025 02:59, Jie Gan wrote:
>>
>>
>> On 6/24/2025 5:59 PM, Jie Gan wrote:
>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
>>> configurations as SA8775p platform.
>>
>> Hi dear maintainers,
>>
>> I just realized it would be more efficient to introduce a common
>> compatible string for SoCs that include two TMC ETR devices.
>>
>> Most of these SoCs share the same CTCU data configuration, such as the
> 
> "Most" basically disqualifies your idea.

Okay, it's not a proper expression.
SoCs included two ETR devices shared same configuration. So I think use 
a common compatible for these SoCs is make sense for me and dont need to 
update the dt-binding again and again...

I will send a new patch to address this idea if it's acceptable.

> 
>> offsets for the ATID and IRQ registers, because they integrate the same
>> version of the CTCU hardware.
>>
>> So I propose introducing a common compatible string,
>> "coresight-ctcu-v2", to simplify the device tree configuration for these
>> platforms.
> 
> This is explained in writing bindings.

Yeah, explained in the code lines..

Thanks,
Jie

> 
> Best regards,
> Krzysztof

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Krzysztof Kozlowski]

On 04/07/2025 10:07, Jie Gan wrote:
> 
>>
>>> offsets for the ATID and IRQ registers, because they integrate the same
>>> version of the CTCU hardware.
>>>
>>> So I propose introducing a common compatible string,
>>> "coresight-ctcu-v2", to simplify the device tree configuration for these
>>> platforms.
>>
>> This is explained in writing bindings.
> 
> Yeah, explained in the code lines..
I meant explained in writing bindings document. Please read writing
bindings first.

Best regards,
Krzysztof

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 7/4/2025 4:10 PM, Krzysztof Kozlowski wrote:
> On 04/07/2025 10:07, Jie Gan wrote:
>>
>>>
>>>> offsets for the ATID and IRQ registers, because they integrate the same
>>>> version of the CTCU hardware.
>>>>
>>>> So I propose introducing a common compatible string,
>>>> "coresight-ctcu-v2", to simplify the device tree configuration for these
>>>> platforms.
>>>
>>> This is explained in writing bindings.
>>
>> Yeah, explained in the code lines..
> I meant explained in writing bindings document. Please read writing
> bindings first.

OK, will check, sorry for the misunderstanding.

Thanks,
Jie

> 
> Best regards,
> Krzysztof

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 7/4/2025 4:14 PM, Jie Gan wrote:
> 
> 
> On 7/4/2025 4:10 PM, Krzysztof Kozlowski wrote:
>> On 04/07/2025 10:07, Jie Gan wrote:
>>>
>>>>
>>>>> offsets for the ATID and IRQ registers, because they integrate the 
>>>>> same
>>>>> version of the CTCU hardware.
>>>>>
>>>>> So I propose introducing a common compatible string,
>>>>> "coresight-ctcu-v2", to simplify the device tree configuration for 
>>>>> these
>>>>> platforms.
>>>>
>>>> This is explained in writing bindings.
>>>
>>> Yeah, explained in the code lines..
>> I meant explained in writing bindings document. Please read writing
>> bindings first.
> 
> OK, will check, sorry for the misunderstanding.

Hi Krzysztof

I checked previous comments and document.
Can you plz help to confirm that we prefer a board specific compatible 
instead of a generic compatible, am right?

Thanks,
Jie

> 
> Thanks,
> Jie
> 
>>
>> Best regards,
>> Krzysztof
> 
> 

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 6/24/2025 5:59 PM, Jie Gan wrote:
> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
> configurations as SA8775p platform.

Gentle ping.

Hi Suzuki, Mike, James, Rob

Can you plz help to review the patch from Coresight view?

Thanks,
Jie

> 
> Changes in V2:
> 1. Add Krzysztof's R-B tag for dt-binding patch.
> 2. Add Konrad's Acked-by tag for dt patch.
> 3. Rebased on tag next-20250623.
> 4. Missed email addresses for coresight's maintainers in V1, loop them.
> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-jie.gan@oss.qualcomm.com/
> 
> Jie Gan (2):
>    dt-bindings: arm: add CTCU device for QCS8300
>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
> 
>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>   2 files changed, 160 insertions(+), 2 deletions(-)
> 

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 7/15/2025 8:41 AM, Jie Gan wrote:
> 
> 
> On 6/24/2025 5:59 PM, Jie Gan wrote:
>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in 
>> binding to utilize
>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 
>> shares same
>> configurations as SA8775p platform.
> 
> Gentle ping.

Gentle ping.

Thanks,
Jie

> 
> Hi Suzuki, Mike, James, Rob
> 
> Can you plz help to review the patch from Coresight view?
> 
> Thanks,
> Jie
> 
>>
>> Changes in V2:
>> 1. Add Krzysztof's R-B tag for dt-binding patch.
>> 2. Add Konrad's Acked-by tag for dt patch.
>> 3. Rebased on tag next-20250623.
>> 4. Missed email addresses for coresight's maintainers in V1, loop them.
>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- 
>> jie.gan@oss.qualcomm.com/
>>
>> Jie Gan (2):
>>    dt-bindings: arm: add CTCU device for QCS8300
>>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>
>>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>>   2 files changed, 160 insertions(+), 2 deletions(-)
>>
> 
> 

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 7/28/2025 9:08 AM, Jie Gan wrote:
> 
> 
> On 7/15/2025 8:41 AM, Jie Gan wrote:
>>
>>
>> On 6/24/2025 5:59 PM, Jie Gan wrote:
>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in 
>>> binding to utilize
>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 
>>> shares same
>>> configurations as SA8775p platform.
>>
>> Gentle ping.
> 
> Gentle ping.

Gentle ping.
Hi Coresight maintainers,

Can you please help to review the patch?

Thanks,
Jie

> 
> Thanks,
> Jie
> 
>>
>> Hi Suzuki, Mike, James, Rob
>>
>> Can you plz help to review the patch from Coresight view?
>>
>> Thanks,
>> Jie
>>
>>>
>>> Changes in V2:
>>> 1. Add Krzysztof's R-B tag for dt-binding patch.
>>> 2. Add Konrad's Acked-by tag for dt patch.
>>> 3. Rebased on tag next-20250623.
>>> 4. Missed email addresses for coresight's maintainers in V1, loop them.
>>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- 
>>> jie.gan@oss.qualcomm.com/
>>>
>>> Jie Gan (2):
>>>    dt-bindings: arm: add CTCU device for QCS8300
>>>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>>
>>>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>>>   2 files changed, 160 insertions(+), 2 deletions(-)
>>>
>>
>>
> 

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Mike Leach]

Hi Jie,

On Tue, 5 Aug 2025 at 05:11, Jie Gan <jie.gan@oss.qualcomm.com> wrote:
>
>
>
> On 7/28/2025 9:08 AM, Jie Gan wrote:
> >
> >
> > On 7/15/2025 8:41 AM, Jie Gan wrote:
> >>
> >>
> >> On 6/24/2025 5:59 PM, Jie Gan wrote:
> >>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in
> >>> binding to utilize
> >>> the compitable of the SA8775p platform becuase the CTCU for QCS8300
> >>> shares same
> >>> configurations as SA8775p platform.
> >>
> >> Gentle ping.
> >
> > Gentle ping.
>
> Gentle ping.
> Hi Coresight maintainers,
>
> Can you please help to review the patch?
>
> Thanks,
> Jie
>
> >
> > Thanks,
> > Jie
> >
> >>
> >> Hi Suzuki, Mike, James, Rob
> >>
> >> Can you plz help to review the patch from Coresight view?
> >>
> >> Thanks,
> >> Jie
> >>
> >>>
> >>> Changes in V2:
> >>> 1. Add Krzysztof's R-B tag for dt-binding patch.
> >>> 2. Add Konrad's Acked-by tag for dt patch.
> >>> 3. Rebased on tag next-20250623.
> >>> 4. Missed email addresses for coresight's maintainers in V1, loop them.
> >>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-
> >>> jie.gan@oss.qualcomm.com/
> >>>
> >>> Jie Gan (2):
> >>>    dt-bindings: arm: add CTCU device for QCS8300
> >>>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
> >>>
> >>>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
> >>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
> >>>   2 files changed, 160 insertions(+), 2 deletions(-)
> >>>
> >>
> >>
> >
>

You need to send a new patch addressing the comments made by Krzysztof..

Regards

Mike
-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 8/5/2025 5:53 PM, Mike Leach wrote:
> Hi Jie,
> 
> On Tue, 5 Aug 2025 at 05:11, Jie Gan <jie.gan@oss.qualcomm.com> wrote:
>>
>>
>>
>> On 7/28/2025 9:08 AM, Jie Gan wrote:
>>>
>>>
>>> On 7/15/2025 8:41 AM, Jie Gan wrote:
>>>>
>>>>
>>>> On 6/24/2025 5:59 PM, Jie Gan wrote:
>>>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in
>>>>> binding to utilize
>>>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300
>>>>> shares same
>>>>> configurations as SA8775p platform.
>>>>
>>>> Gentle ping.
>>>
>>> Gentle ping.
>>
>> Gentle ping.
>> Hi Coresight maintainers,
>>
>> Can you please help to review the patch?
>>
>> Thanks,
>> Jie
>>
>>>
>>> Thanks,
>>> Jie
>>>
>>>>
>>>> Hi Suzuki, Mike, James, Rob
>>>>
>>>> Can you plz help to review the patch from Coresight view?
>>>>
>>>> Thanks,
>>>> Jie
>>>>
>>>>>
>>>>> Changes in V2:
>>>>> 1. Add Krzysztof's R-B tag for dt-binding patch.
>>>>> 2. Add Konrad's Acked-by tag for dt patch.
>>>>> 3. Rebased on tag next-20250623.
>>>>> 4. Missed email addresses for coresight's maintainers in V1, loop them.
>>>>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-
>>>>> jie.gan@oss.qualcomm.com/
>>>>>
>>>>> Jie Gan (2):
>>>>>     dt-bindings: arm: add CTCU device for QCS8300
>>>>>     arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>>>>
>>>>>    .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>>>>    arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>>>>>    2 files changed, 160 insertions(+), 2 deletions(-)
>>>>>
>>>>
>>>>
>>>
>>
> 
> You need to send a new patch addressing the comments made by Krzysztof..

Hi Mike,

I just proposed an idea to add a common compatible for CTCU device, its 
not about the patch series itself. We dropped the idea and prefer to add 
the board specific compatible for each platform.

Thanks,
Jie

> 
> Regards
> 
> Mike

Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan]

On 8/5/2025 6:25 PM, Jie Gan wrote:
> 
> 
> On 8/5/2025 5:53 PM, Mike Leach wrote:
>> Hi Jie,
>>
>> On Tue, 5 Aug 2025 at 05:11, Jie Gan <jie.gan@oss.qualcomm.com> wrote:
>>>
>>>
>>>
>>> On 7/28/2025 9:08 AM, Jie Gan wrote:
>>>>
>>>>
>>>> On 7/15/2025 8:41 AM, Jie Gan wrote:
>>>>>
>>>>>
>>>>> On 6/24/2025 5:59 PM, Jie Gan wrote:
>>>>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in
>>>>>> binding to utilize
>>>>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300
>>>>>> shares same
>>>>>> configurations as SA8775p platform.
>>>>>
>>>>> Gentle ping.
>>>>
>>>> Gentle ping.
>>>
>>> Gentle ping.
>>> Hi Coresight maintainers,
>>>
>>> Can you please help to review the patch?
>>>
>>> Thanks,
>>> Jie
>>>
>>>>
>>>> Thanks,
>>>> Jie
>>>>
>>>>>
>>>>> Hi Suzuki, Mike, James, Rob
>>>>>
>>>>> Can you plz help to review the patch from Coresight view?
>>>>>
>>>>> Thanks,
>>>>> Jie
>>>>>
>>>>>>
>>>>>> Changes in V2:
>>>>>> 1. Add Krzysztof's R-B tag for dt-binding patch.
>>>>>> 2. Add Konrad's Acked-by tag for dt patch.
>>>>>> 3. Rebased on tag next-20250623.
>>>>>> 4. Missed email addresses for coresight's maintainers in V1, loop 
>>>>>> them.
>>>>>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1-
>>>>>> jie.gan@oss.qualcomm.com/
>>>>>>
>>>>>> Jie Gan (2):
>>>>>>     dt-bindings: arm: add CTCU device for QCS8300
>>>>>>     arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>>>>>
>>>>>>    .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>>>>>    arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 +++++++++++ 
>>>>>> +++++++
>>>>>>    2 files changed, 160 insertions(+), 2 deletions(-)
>>>>>>
>>>>>
>>>>>
>>>>
>>>
>>
>> You need to send a new patch addressing the comments made by Krzysztof..
> 
> Hi Mike,
> 
> I just proposed an idea to add a common compatible for CTCU device, its 
> not about the patch series itself. We dropped the idea and prefer to add 
> the board specific compatible for each platform.
> 
> Thanks,
> Jie

Hi Suzuki, Mike, James

We already have the tag from dt-binding and dt maintainers. We haven't 
additional modification for this patch series. Can you please help to 
review the patch series from Coresight View?

Thanks,
Jie

> 
>>
>> Regards
>>
>> Mike
> 
>