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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDAwNiBTYWx0ZWRfX0LlIGY65+Tuj A3hC932Urd8wZBqHVcctcl3XYoPb4vtdnj4Yf3h4p/Ewwz21z9AE+tCn2NDsLoMdtT6n0oTYDTo P2Fge7jz5EB5kGGLxxHidgfM3UeJgBIB4rOgPEMmWlg3WqlW0Cbsx2kDOqMbBNVxYd+JTYhU2ki W4gVWV76X4zk+ueAv6wQhHhd2dK+zF5P/L7chDkhsBeHDjtlwYNnHCV/NijNaq2OQDYldtW2JTK jvg+xue5LLdaTiJ+CamCO4WkvQoEQXY7OYZyEAvwYEw3AMu8NDT3y0lK8zGGoEAexZCFtwhTDH0 jJ3OiVohQ6B+Jtq89xoxWYOaLl4RdGxPdFa5JjeHX7kEk4D3FpjgC/fzbV1F0e0onj+t02csnXg 0rT0W2XZxFHa4JsaNJepZNFW5qQoInaKMrzQMsTOvdHOU0b0ETbcm1a1UGODg4QZsIGXNnRq9Wx wFLnyUzBHQwjojllA8A== X-Authority-Analysis: v=2.4 cv=MuhfKmae c=1 sm=1 tr=0 ts=69a63ea4 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=BiHMn5M11h/vNwziJwzFrg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=gEfo2CItAAAA:8 a=KKAkSRfTAAAA:8 a=VwQbUJbxAAAA:8 a=ZuF4YGRwA1bEcIVO1K4A:9 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 a=sptkURWiP4Gy88Gu7hUp:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: a0dnBw-X6CAGnIMmgJ0eDrKHsoEyLQkS X-Proofpoint-GUID: a0dnBw-X6CAGnIMmgJ0eDrKHsoEyLQkS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-02_05,2026-03-02_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030006 Hi Bryan, On 2/26/2026 4:34 AM, Bryan O'Donoghue wrote: > Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 > PHY devices. > > The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices > have their own pinouts on the SoC as well as their own individual voltage > rails. > > The need to model voltage rails on a per-PHY basis leads us to define > CSIPHY devices as individual nodes. > > Two nice outcomes in terms of schema and DT arise from this change. > > 1. The ability to define on a per-PHY basis voltage rails. > 2. The ability to require those voltage. > > We have had a complete bodge upstream for this where a single set of > voltage rail for all CSIPHYs has been buried inside of CAMSS. > > Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in > CAMSS parlance, the CSIPHY devices should be individually modelled. > > Signed-off-by: Bryan O'Donoghue > --- > .../bindings/phy/qcom,x1e80100-csi2-phy.yaml | 114 +++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > new file mode 100644 > index 0000000000000..c937d26ccbda9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml > @@ -0,0 +1,114 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-csi2-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm CSI2 PHY > + > +maintainers: > + - Bryan O'Donoghue > + > +description: > + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors > + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY > + modes. > + > +properties: > + compatible: > + const: qcom,x1e80100-csi2-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 1 > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: csiphy > + - const: csiphy_timer > + - const: camnoc_axi > + - const: cpas_ahb > + > + interrupts: > + maxItems: 1 > + > + operating-points-v2: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + vdda-0p8-supply: > + description: Phandle to a 0.8V regulator supply to a PHY. > + > + vdda-1p2-supply: > + description: Phandle to 1.2V regulator supply to a PHY. > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - interrupts > + - operating-points-v2 > + - power-domains > + - vdda-0p8-supply > + - vdda-1p2-supply > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + csiphy@ace4000 { > + compatible = "qcom,x1e80100-csi2-phy"; > + reg = <0x0ace4000 0x2000>; > + #phy-cells = <1>; > + > + clocks = <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>; > + clock-names = "csiphy", > + "csiphy_timer", > + "camnoc_axi", > + "cpas_ahb"; > + > + operating-points-v2 = <&csiphy_opp_table>; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; As we are cleaning up the PHY device nodes, we should consider fixing the power domains as well. Although TOP GDSC is defined as a power domain, it is not the power source for the PHY devices. Rather, it is the MMCX, MXC and optionally MXA based on the architecture (Refer to 'Voltage rail' column for PHY clocks in IPCAT). There is no parent-child relationship between the TOP GDSC and these in the clock driver and it was just working as the required power rails are getting enabled by/for other MM devices. > + > + vdda-0p8-supply = <&vreg_l2c_0p8>; > + vdda-1p2-supply = <&vreg_l1c_1p2>; > + }; > + > + csiphy_opp_table: opp-table-csiphy { > + compatible = "operating-points-v2"; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_low_svs_d1>; > + }; > + > + opp-400000000 { > + opp-hz = /bits/ 64 <400000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-480000000 { > + opp-hz = /bits/ 64 <480000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + }; > Thanks, Vijay.