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Fri, 22 Nov 2024 06:07:17 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AM67GPf029964 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Nov 2024 06:07:16 GMT Received: from [10.64.68.72] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 21 Nov 2024 22:07:10 -0800 Message-ID: Date: Fri, 22 Nov 2024 14:07:08 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: qcs615: add UFS node To: Dmitry Baryshkov CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Bjorn Andersson , Konrad Dybcio , Vinod Koul , "Kishon Vijay Abraham I" , Alim Akhtar , Avri Altman , Bart Van Assche , "Andy Gross" , , , , , , , , , References: <20241119022050.2995511-1-quic_liuxin@quicinc.com> <20241119022050.2995511-3-quic_liuxin@quicinc.com> <45cb4thpg6mrtxiwdb333w2jxgtpw426akik2l3f7qv57dvwmm@kma6vrglbrjh> From: Xin Liu In-Reply-To: <45cb4thpg6mrtxiwdb333w2jxgtpw426akik2l3f7qv57dvwmm@kma6vrglbrjh> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Q3ijIbtUjn_N8OD4cNVIln5lLAvnoS0E X-Proofpoint-GUID: Q3ijIbtUjn_N8OD4cNVIln5lLAvnoS0E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 clxscore=1011 phishscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 spamscore=0 adultscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411220049 在 2024/11/22 1:00, Dmitry Baryshkov 写道: > On Tue, Nov 19, 2024 at 10:20:49AM +0800, Xin Liu wrote: >> From: Sayali Lokhande >> >> Add the UFS Host Controller node and its PHY for QCS615 SoC. >> >> Signed-off-by: Sayali Lokhande >> Co-developed-by: Xin Liu >> Signed-off-by: Xin Liu >> --- >> arch/arm64/boot/dts/qcom/qcs615.dtsi | 112 +++++++++++++++++++++++++++ >> 1 file changed, 112 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> index 590beb37f441..ceceafb2e71f 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >> @@ -458,6 +458,118 @@ mmss_noc: interconnect@1740000 { >> qcom,bcm-voters = <&apps_bcm_voter>; >> }; >> >> + ufs_mem_hc: ufshc@1d84000 { >> + compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >> + reg = <0x0 0x01d84000 0x0 0x3000>, <0x0 0x01d90000 0x0 0x8000>; > > Please consider splitting to have one entry per line (and reg-names > too). Thank you for your comments. I will fix it next version. > >> + reg-names = "std", "ice"; >> + >> + interrupts = ; >> + >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "core_clk_ice", > > Wrong indentation > > Other than that LGTM. > Thank you for your comments. I will fix it next version. > >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk"; >> + >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + operating-points-v2 = <&ufs_opp_table>; >> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "ufs-ddr", >> + "cpu-ufs"; >> + >> + power-domains = <&gcc UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x300 0x0>; >> + dma-coherent; >> + >> + lanes-per-direction = <1>; >> + >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + >> + #reset-cells = <1>; >> + >> + status = "disabled"; >> + >> + ufs_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-50000000 { >> + opp-hz = /bits/ 64 <50000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <37500000>, >> + /bits/ 64 <75000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <75000000>, >> + /bits/ 64 <150000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-200000000 { >> + opp-hz = /bits/ 64 <200000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <150000000>, >> + /bits/ 64 <300000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> + >> + ufs_mem_phy: phy@1d87000 { >> + compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; >> + reg = <0x0 0x01d87000 0x0 0xe00>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> + <&gcc GCC_UFS_MEM_CLKREF_CLK>; >> + clock-names = "ref", >> + "ref_aux", >> + "qref"; >> + >> + power-domains = <&gcc UFS_PHY_GDSC>; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x0 0x01f40000 0x0 0x20000>; >> -- >> 2.34.1 >> >> >> -- >> linux-phy mailing list >> linux-phy@lists.infradead.org >> https://lists.infradead.org/mailman/listinfo/linux-phy >