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Tue, 07 Apr 2026 13:04:41 -0700 (PDT) X-Received: by 2002:a17:902:d2c8:b0:2b2:523f:50d with SMTP id d9443c01a7336-2b281802cacmr192446915ad.29.1775592280993; Tue, 07 Apr 2026 13:04:40 -0700 (PDT) Received: from [192.168.1.8] ([106.222.229.237]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2749cbce2sm178975185ad.79.2026.04.07.13.04.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Apr 2026 13:04:40 -0700 (PDT) Message-ID: Date: Wed, 8 Apr 2026 01:34:32 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v2 3/6] drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC To: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Bjorn Andersson References: <20260402-adreno-810-v2-0-ce337ca87a9e@pm.me> <20260402-adreno-810-v2-3-ce337ca87a9e@pm.me> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20260402-adreno-810-v2-3-ce337ca87a9e@pm.me> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=dO6WXuZb c=1 sm=1 tr=0 ts=69d5635a cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=oIjhDLspr5RTlLLUpj0f1A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=zzMsImXSMt5mrjmxLFkA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: CN2JpbgAKZD3dzaP-kvN62Q12Mkvu5J9 X-Proofpoint-ORIG-GUID: CN2JpbgAKZD3dzaP-kvN62Q12Mkvu5J9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDE4MiBTYWx0ZWRfX1GFFu2tsXXwB 1n9rkh1yGVdphbxn39qYkxO85WZ1X0QvD+XaH2hxvQ9UIuzs+ZtUejbMnu7+Gtn0oGOpbGuK1zI ExaWmqVmSuUOnHCSkbKIvHuQTzDJJWM6fDD9y+ysGXH6rRQkTlZJD7jZeti+CSZihABzr/c1kaQ 5/Ivacya4wWfmBAVB1e8L1erz+J62jWmbUyW5ojeD68AMQezKWHFYSQbtnKMhbWnwChMBciASvG u8g7ZgtXoRQvqjXukQ56u+bCeUMw4zaDxv4MflbQLEeBbGD/PP2b0m2feNs6a0aMUu8ncjwM58H QCnB9Jl2E61DeDKiZdz23l/W79MJfeVFsRdPdNgkvCMKXleYyPWA0CjQvBByZOf1wHTNWy7cR9K 251it869nEa+LOY+A7KEvHAMuHLEJSvhImsQQbXLmwC4esNYqE9URwR3rUIMnK0hSz4974gpl++ NhSC32Df0vJ03f6XRgw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_04,2026-04-07_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070182 On 4/3/2026 4:39 AM, Alexander Koskovich wrote: > Platforms without a LLCC (e.g. milos) still need to be able to read and > write to the cx_mem region. Previously if LLCC slices were unavailable > the cx_misc_mmio mapping was overwritten with ERR_PTR, causing a crash > when the GMU later accessed cx_mem. > > Move the cx_misc_mmio mapping out of a6xx_llc_slices_init() into > a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Alexander Koskovich > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++------------------- > 1 file changed, 17 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 9847f83b92af..d691ad1f88b3 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu) > struct msm_gpu *gpu = &adreno_gpu->base; > u32 cntl1_regval = 0; > > - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) > + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) > return; > > if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { > @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_gpu) > struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > struct msm_gpu *gpu = &adreno_gpu->base; > > - if (IS_ERR(a6xx_gpu->cx_misc_mmio)) > + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) > return; > > if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { > @@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu) > static void a6xx_llc_slices_init(struct platform_device *pdev, > struct a6xx_gpu *a6xx_gpu, bool is_a7xx) > { > - struct device_node *phandle; > - > /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ > if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) > return; > > - /* > - * There is a different programming path for A6xx targets with an > - * mmu500 attached, so detect if that is the case > - */ > - phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); > - a6xx_gpu->have_mmu500 = (phandle && > - of_device_is_compatible(phandle, "arm,mmu-500")); > - of_node_put(phandle); > - > - if (is_a7xx || !a6xx_gpu->have_mmu500) > - a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem"); > - else > - a6xx_gpu->cx_misc_mmio = NULL; > - > a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU); > a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW); > - > - if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) > - a6xx_gpu->cx_misc_mmio = ERR_PTR(-EINVAL); > } > > #define GBIF_CLIENT_HALT_MASK BIT(0) > @@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > struct platform_device *pdev = priv->gpu_pdev; > struct adreno_platform_config *config = pdev->dev.platform_data; > const struct adreno_info *info = config->info; > + struct device_node *phandle; > struct device_node *node; > struct a6xx_gpu *a6xx_gpu; > struct adreno_gpu *adreno_gpu; > @@ -2656,6 +2638,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) > > a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); > > + /* > + * There is a different programming path for A6xx targets with an > + * mmu500 attached, so detect if that is the case > + */ > + phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0); > + a6xx_gpu->have_mmu500 = (phandle && > + of_device_is_compatible(phandle, "arm,mmu-500")); > + of_node_put(phandle); > + > + if (is_a7xx || !a6xx_gpu->have_mmu500) Instead of this check, I feel it is better to just add a WARN_ONCE(a6xx_gpu->cx_misc_mmio) in the a6xx_cx_misc_* io accessors. Then "a6xx_gpu->have_mmu500" init can be moved to the llc_init(). But that is outside the scope of this series. Reviewed-by: Akhil P Oommen -Akhil > + a6xx_gpu->cx_misc_mmio = msm_ioremap(pdev, "cx_mem"); > + else > + a6xx_gpu->cx_misc_mmio = NULL; > + > ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); > if (ret) { > a6xx_llc_slices_destroy(a6xx_gpu); >