From: "Aiqun(Maria) Yu" <aiqun.yu@oss.qualcomm.com>
To: Jingyi Wang <jingyi.wang@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Taniya Das <quic_tdas@quicinc.com>,
Taniya Das <taniya.das@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com,
yijie.yang@oss.qualcomm.com
Subject: Re: [PATCH 5/9] clk: qcom: Update TCSR clock driver for Kaanapali
Date: Mon, 20 Oct 2025 18:11:53 +0800 [thread overview]
Message-ID: <c9e27a9e-2274-4b1f-9953-ca012ba2615f@oss.qualcomm.com> (raw)
In-Reply-To: <20250924-knp-clk-v1-5-29b02b818782@oss.qualcomm.com>
On 9/25/2025 6:58 AM, Jingyi Wang wrote:
> From: Taniya Das <taniya.das@oss.qualcomm.com>
>
> The TCSR clock controller found on Kaanapali provides refclks for PCIE, USB
> and UFS. Update the SM8750 driver to fix the offsets for the clocks.
>
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---
> drivers/clk/qcom/tcsrcc-sm8750.c | 34 ++++++++++++++++++++++++++++++++--
> 1 file changed, 32 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/tcsrcc-sm8750.c b/drivers/clk/qcom/tcsrcc-sm8750.c
> index 242e320986ef..f905f3824d7e 100644
> --- a/drivers/clk/qcom/tcsrcc-sm8750.c
> +++ b/drivers/clk/qcom/tcsrcc-sm8750.c
> @@ -100,21 +100,51 @@ static const struct regmap_config tcsr_cc_sm8750_regmap_config = {
> .fast_io = true,
> };
>
> +static const struct regmap_config tcsr_cc_kaanapali_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x18,
> + .fast_io = true,
> +};
> +
> static const struct qcom_cc_desc tcsr_cc_sm8750_desc = {
> .config = &tcsr_cc_sm8750_regmap_config,
> .clks = tcsr_cc_sm8750_clocks,
> .num_clks = ARRAY_SIZE(tcsr_cc_sm8750_clocks),
> };
>
> +static const struct qcom_cc_desc tcsr_cc_kaanapali_desc = {
> + .config = &tcsr_cc_kaanapali_regmap_config,
> + .clks = tcsr_cc_sm8750_clocks,
> + .num_clks = ARRAY_SIZE(tcsr_cc_sm8750_clocks),
> +};
> +
> static const struct of_device_id tcsr_cc_sm8750_match_table[] = {
> - { .compatible = "qcom,sm8750-tcsr" },
> + { .compatible = "qcom,kaanapali-tcsr", .data = &tcsr_cc_kaanapali_desc},
> + { .compatible = "qcom,sm8750-tcsr", .data = &tcsr_cc_sm8750_desc},
> { }
> };
> MODULE_DEVICE_TABLE(of, tcsr_cc_sm8750_match_table);
>
> static int tcsr_cc_sm8750_probe(struct platform_device *pdev)
> {
> - return qcom_cc_probe(pdev, &tcsr_cc_sm8750_desc);
> + const struct qcom_cc_desc *desc;
> +
> + desc = device_get_match_data(&pdev->dev);
> +
> + if (device_is_compatible(&pdev->dev, "qcom,kaanapali-tcsr")) {
> + tcsr_ufs_clkref_en.halt_reg = 0x10;
> + tcsr_ufs_clkref_en.clkr.enable_reg = 0x10;
> +
> + tcsr_usb2_clkref_en.halt_reg = 0x18;
> + tcsr_usb2_clkref_en.clkr.enable_reg = 0x18;
> +
> + tcsr_usb3_clkref_en.halt_reg = 0x8;
> + tcsr_usb3_clkref_en.clkr.enable_reg = 0x8;
> + }
> +
> + return qcom_cc_probe(pdev, desc);
> }
>
> static struct platform_driver tcsr_cc_sm8750_driver = {
>
Remind to review the change.
--
Thx and BRs,
Aiqun(Maria) Yu
next prev parent reply other threads:[~2025-10-20 10:12 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-24 22:58 [PATCH 0/9] Add support for Clock controllers for Kaanapali Jingyi Wang
2025-09-24 22:58 ` [PATCH 1/9] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC " Jingyi Wang
2025-10-12 3:06 ` Krzysztof Kozlowski
2025-09-24 22:58 ` [PATCH 2/9] dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller Jingyi Wang
2025-10-12 3:07 ` Krzysztof Kozlowski
2025-09-24 22:58 ` [PATCH 3/9] dt-bindings: clock: qcom: Add Kaanapali Global clock controller Jingyi Wang
2025-10-12 3:06 ` Krzysztof Kozlowski
2025-09-24 22:58 ` [PATCH 4/9] clk: qcom: rpmh: Add support for Kaanapali rpmh clocks Jingyi Wang
2025-10-20 10:11 ` Aiqun(Maria) Yu
2025-10-20 10:25 ` Krzysztof Kozlowski
2025-10-20 10:59 ` Dmitry Baryshkov
2025-10-23 6:35 ` Taniya Das
2025-09-24 22:58 ` [PATCH 5/9] clk: qcom: Update TCSR clock driver for Kaanapali Jingyi Wang
2025-10-20 10:11 ` Aiqun(Maria) Yu [this message]
2025-10-20 10:27 ` Krzysztof Kozlowski
2025-10-20 11:03 ` Dmitry Baryshkov
2025-10-23 6:56 ` Taniya Das
2025-10-22 21:47 ` Bjorn Andersson
2025-09-24 22:58 ` [PATCH 6/9] clk: qcom: Add support for Global clock controller on Kaanapali Jingyi Wang
2025-09-25 21:26 ` Dmitry Baryshkov
2025-09-24 22:58 ` [PATCH 7/9] clk: qcom: clk-alpha-pll: Update the PLL support for cal_l Jingyi Wang
2025-09-25 9:30 ` Konrad Dybcio
2025-09-25 21:28 ` Dmitry Baryshkov
2025-09-24 22:59 ` [PATCH 8/9] clk: qcom: clk-alpha-pll: Add support for controlling Pongo EKO_T PLL Jingyi Wang
2025-09-25 12:46 ` Konrad Dybcio
2025-09-24 22:59 ` [PATCH 9/9] clk: qcom: clk-alpha-pll: Add support for controlling Rivian PLL Jingyi Wang
2025-09-25 12:46 ` Konrad Dybcio
2025-10-22 21:53 ` [PATCH 0/9] Add support for Clock controllers for Kaanapali Bjorn Andersson
2025-10-23 8:42 ` Taniya Das
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