Re: [PATCH v2 1/2] clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC

[Konrad Dybcio <konrad.dybcio@linaro.org>]

On 1.02.2023 18:23, Dmitry Baryshkov wrote:
> The gdsc_init() function will rewrite the CLK_DIS_WAIT field while
> registering the GDSC (writing the value 0x2 by default). This will
> override the setting done in the driver's probe function.
> 
> Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe
> function.
> 
> Fixes: 745ff069a49c ("clk: qcom: Add graphics clock controller driver for SC7180")
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  drivers/clk/qcom/gpucc-sc7180.c | 7 +------
>  1 file changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c
> index d738251cba17..6839b4b71a2f 100644
> --- a/drivers/clk/qcom/gpucc-sc7180.c
> +++ b/drivers/clk/qcom/gpucc-sc7180.c
> @@ -21,8 +21,6 @@
>  #define CX_GMU_CBCR_SLEEP_SHIFT		4
>  #define CX_GMU_CBCR_WAKE_MASK		0xF
>  #define CX_GMU_CBCR_WAKE_SHIFT		8
> -#define CLK_DIS_WAIT_SHIFT		12
> -#define CLK_DIS_WAIT_MASK		(0xf << CLK_DIS_WAIT_SHIFT)
>  
>  enum {
>  	P_BI_TCXO,
> @@ -160,6 +158,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
>  static struct gdsc cx_gdsc = {
>  	.gdscr = 0x106c,
>  	.gds_hw_ctrl = 0x1540,
> +	.clk_dis_wait_val = 8,
>  	.pd = {
>  		.name = "cx_gdsc",
>  	},
> @@ -242,10 +241,6 @@ static int gpu_cc_sc7180_probe(struct platform_device *pdev)
>  	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
>  	regmap_update_bits(regmap, 0x1098, mask, value);
>  
> -	/* Configure clk_dis_wait for gpu_cx_gdsc */
> -	regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
> -						8 << CLK_DIS_WAIT_SHIFT);
> -
>  	return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
>  }
>