Re: [PATCH RFT 2/3] arm64: dts: qcom: glymur: Add USB related nodes

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 1/26/26 3:31 PM, Abel Vesa wrote:
> On 26-01-13 14:13:32, Konrad Dybcio wrote:
>> On 1/13/26 1:33 PM, Abel Vesa wrote:
>>> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>>>
>>> The Glymur USB system contains 3 USB type C ports, 1 USB multiport
>>> controller and a USB 2.0 only controller. This encompasses 5 SS USB QMP
>>> PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS
>>> DWC3 based, so describe them as flattened DWC3 QCOM nodes.
>>>
>>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>>> Co-developed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>
>> [...]
>>
>>>  
>>> +		usb_mp_hsphy0: phy@fa1000 {
>>> +			compatible = "qcom,glymur-m31-eusb2-phy",
>>> +				     "qcom,sm8750-m31-eusb2-phy";
>>> +
>>> +			reg = <0 0x00fa1000 0 0x29c>;
>>> +			#phy-cells = <0>;
>>> +
>>> +			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
>>> +			clock-names = "ref";
>>> +
>>> +			resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
>>> +
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		usb_mp_hsphy1: phy@fa2000  {
>>> +			compatible = "qcom,glymur-m31-eusb2-phy",
>>> +				     "qcom,sm8750-m31-eusb2-phy";
>>> +
>>> +			reg = <0 0x00fa2000 0 0x29c>;
>>> +			#phy-cells = <0>;
>>> +
>>> +			clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
>>> +			clock-names = "ref";
>>> +
>>> +			resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
>>> +
>>> +			status = "disabled";
>>> +		};
>>
>>
>> [...]
>>
>>> +		usb1_ss0_hsphy: phy@fd3000 {
>>
>> Let's not repeat the mess introduced in hamoa..
>>
>> Perhaps let's fall back to usb_0 etc.?
> 
> Sure. So then:
> 
> USB SS[0-2]              -> usb_[0-2]
> USB MP                   -> usb_mp
> USB 2.0 (USB20S in docs) -> ?

usb_hs

Konrad