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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: IywfiQxpCGs_-_0jIq5361rNBO0Wzkz7 X-Proofpoint-ORIG-GUID: IywfiQxpCGs_-_0jIq5361rNBO0Wzkz7 X-Authority-Analysis: v=2.4 cv=UtRT8ewB c=1 sm=1 tr=0 ts=6a54d6a9 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=AMBhOB7pGyomvzLA2OYA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEzMDEyOCBTYWx0ZWRfXwET74p1XXCBM i6RJz5k95Vt4ifMVufHUodKzMqItGb6HPf6ZbvNBQAvXl3veMuLbUbS9lTdtKKkYoeE60bSozT4 nL1VKF7V6z2Cf8Wx6lchDEr56S1y9rQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEzMDEyOCBTYWx0ZWRfX/0PkbGmYEzwV 7GuNiSORMaXW63t4rdquZIcO8JscSN5/AbdxHhQw2uerpPwKrFL9PmsP0k5gP5hUo7fx+X01Ywc JNzZuaTzYHwgJ/FW9fsxDUhFMvWlfrGb/a217hr9bFZwB+MjjyufENYPW9bQXiLvDEEsi6XLrLn TGNuFyZ4wq+GcB6aNcQgWQp0Rapng5rqE85bExxghY1p5Ez6hIREqus4fq6S47coKP18qcU9cu5 /8TIvo2JEOceNn0lWexbOap88c1ZIARyv4eDrzIpC/hv05pUXPaxDcpKg9wTCLu2o1yYzRzs/Fi kroLofTfcCoG0Fjsp5OmnY2OzNbFJ63NY7qR2PcBEnGgQzWWveroXjfJz+rikMNoxbR5lwtDbIR 3vySSO49lO7WCdSSOJxSJpgrSS3PxQBkoKRGAGYXvY2XBei4kDE16CRJSiGTPriXKxS2UFiTYne RqSke+JuLrx5v0qkNMg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-13_03,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607130128 On 7/13/26 2:07 PM, Imran Shaik wrote: > > > On 09-07-2026 05:30 pm, Konrad Dybcio wrote: >> On 7/8/26 8:25 PM, Imran Shaik wrote: >>> Add support for Audio Core Clock Controller (AudioCoreCC) and Audio Core >>> CSR nodes on Qualcomm Shikra SoC. The Audio Core Clocks and Resets support >>> differs across Shikra variants based on Audio subsystem enablement as >>> follows: >>> - CQM variant: The QAIF driver runs on HLOS, hence both clocks and resets >>> are required to be supported on HLOS. >>> - CQS variant: The QAIF driver runs on the Modem, and required clocks are >>> handled on Modem, so from HLOS only resets are needed. >>> - IQS variant: no soundwire codes, hence no clocks/resets are needed. >>> >>> Signed-off-by: Imran Shaik >>> --- >> >> For the sake of simplification, can the resets be enabled >> globally by default? >> > > By default (PoR), those resets are under HW control. For audio use cases, software desserts/asserts for switching to SW control. Hence, these cannot be enabled globally by default. What does enabling the provider node have to do with changing the state of the resources? FWIW there's nothing like reset_sync_state Konrad