Re: [PATCH v5 3/4] arm64: dts: qcom: Introduce Glymur base dtsi

[Pankaj Patil <pankaj.patil@oss.qualcomm.com>]

On 1/22/2026 4:11 PM, Dmitry Baryshkov wrote:
> On Thu, Jan 22, 2026 at 12:15:17PM +0530, Pankaj Patil wrote:
>> On 1/22/2026 6:52 AM, Dmitry Baryshkov wrote:
>>> On Thu, Jan 22, 2026 at 12:05:13AM +0530, Pankaj Patil wrote:
>>>> Introduce the base device tree support for Glymur – Qualcomm's
>>>> next-generation compute SoC. The new glymur.dtsi describes the core SoC
>>>> components, including:
>>>>
>>>> - CPUs and CPU topology
>>>> - Interrupt controller and TLMM
>>>> - GCC,DISPCC and RPMHCC clock controllers
>>>> - Reserved memory and interconnects
>>>> - APPS and PCIe SMMU and firmware SCM
>>>> - Watchdog, RPMHPD, APPS RSC and SRAM
>>>> - PSCI and PMU nodes
>>>> - QUPv3 serial engines
>>>> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS
>>>> - PDP0 mailbox, IPCC and AOSS
>>>> - Display clock controller
>>>> - SPMI PMIC arbiter with SPMI0/1/2 buses
>>>> - SMP2P nodes
>>>> - TSENS and thermal zones (8 instances, 92 sensors)
>>>>
>>>> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104,
>>>> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur
>>>>
>>>> Enabled PCIe controllers and associated PHY to support boot to
>>>> shell with nvme storage,
>>>> List of PCIe instances enabled:
>>>>
>>>> - PCIe3b
>>>> - PCIe4
>>>> - PCIe5
>>>> - PCIe6
>>>>
>>>> Co-developed-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>>> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>>>> Co-developed-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
>>>> Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com>
>>>> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>>>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>>>> Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>>> Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
>>>> Co-developed-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>>> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
>>>> Co-developed-by: Abel Vesa <abel.vesa@linaro.org>
>>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>>> Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>>>> Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
>>>> Co-developed-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>>> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
>>>> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/glymur.dtsi         | 6122 ++++++++++++++++++++++++++
>>>>  arch/arm64/boot/dts/qcom/pmcx0102.dtsi       |  107 +
>>>>  arch/arm64/boot/dts/qcom/pmh0101.dtsi        |   45 +
>>>>  arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi |   83 +
>>>>  arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi |   83 +
>>>>  arch/arm64/boot/dts/qcom/pmk8850.dtsi        |   70 +
>>>>  arch/arm64/boot/dts/qcom/smb2370.dtsi        |   45 +
>>>>  7 files changed, 6555 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>>> new file mode 100644
>>>> index 000000000000..c0ecc64202c7
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
>>>> +
>>>> +		pmh0101-thermal {
>>>
>>> Why do we have PMIC thermal zones as a part of SoC DTSI?
>>
>> There were comments on v3 about moving them to out of board dts,
>> https://lore.kernel.org/all/aUko20ORsgrlZrIn@linaro.org/
>> glymur-pmics.dtsi was dropped in v4, the changes were moved to glymur.dtsi
> 
> Anyway, the PMICS (nor their thermal zones) are not a part of the SoC.
> As such, they don't belong to glymur.dtsi.
> 

Moving pmic thermal zones to their respective pmic dtsi files in next revision