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Sat, 30 Nov 2024 20:40:10 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AUKe9Vf000494 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 30 Nov 2024 20:40:09 GMT Received: from [10.216.58.247] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 30 Nov 2024 12:40:03 -0800 Message-ID: Date: Sun, 1 Dec 2024 02:09:59 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/7] drm/msm: adreno: add defines for gpu & gmu frequency table sizes To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , "Dmitry Baryshkov" , Marijn Suijten , David Airlie , "Simona Vetter" , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , References: <20241128-topic-sm8x50-gpu-bw-vote-v3-0-81d60c10fb73@linaro.org> <20241128-topic-sm8x50-gpu-bw-vote-v3-1-81d60c10fb73@linaro.org> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <20241128-topic-sm8x50-gpu-bw-vote-v3-1-81d60c10fb73@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Cw0hmv0RyJZ5DAUWt21PmKMBRbJK7duU X-Proofpoint-ORIG-GUID: Cw0hmv0RyJZ5DAUWt21PmKMBRbJK7duU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 clxscore=1015 bulkscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2411300175 On 11/28/2024 3:55 PM, Neil Armstrong wrote: > Even if the code uses ARRAY_SIZE() to fill those tables, > it's still a best practice to not use magic values for > tables in structs. > > Suggested-by: Dmitry Baryshkov > Signed-off-by: Neil Armstrong Reviewed-by: Akhil P Oommen -Akhil > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > index b4a79f88ccf45cfe651c86d2a9da39541c5772b3..88f18ea6a38a08b5b171709e5020010947a5d347 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h > @@ -19,6 +19,9 @@ struct a6xx_gmu_bo { > u64 iova; > }; > > +#define GMU_MAX_GX_FREQS 16 > +#define GMU_MAX_CX_FREQS 4 > + > /* > * These define the different GMU wake up options - these define how both the > * CPU and the GMU bring up the hardware > @@ -79,12 +82,12 @@ struct a6xx_gmu { > int current_perf_index; > > int nr_gpu_freqs; > - unsigned long gpu_freqs[16]; > - u32 gx_arc_votes[16]; > + unsigned long gpu_freqs[GMU_MAX_GX_FREQS]; > + u32 gx_arc_votes[GMU_MAX_GX_FREQS]; > > int nr_gmu_freqs; > - unsigned long gmu_freqs[4]; > - u32 cx_arc_votes[4]; > + unsigned long gmu_freqs[GMU_MAX_CX_FREQS]; > + u32 cx_arc_votes[GMU_MAX_CX_FREQS]; > > unsigned long freq; > >