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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac2a6c9a537sm257191266b.71.2025.03.11.02.48.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Mar 2025 02:48:59 -0700 (PDT) Message-ID: Date: Tue, 11 Mar 2025 10:48:55 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] arm64: dts: qcom: qcs615: enable pcie To: Ziyue Zhang , bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org Cc: quic_qianyu@quicinc.com, quic_krichai@quicinc.com, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20250310065613.151598-1-quic_ziyuzhan@quicinc.com> <20250310065613.151598-3-quic_ziyuzhan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250310065613.151598-3-quic_ziyuzhan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 1MVTT7CacCHJaee6_VW0BnMWBrzoB1Zb X-Authority-Analysis: v=2.4 cv=fZ9Xy1QF c=1 sm=1 tr=0 ts=67d0070d cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=6X6hr80gjlHG-dsRnmcA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 1MVTT7CacCHJaee6_VW0BnMWBrzoB1Zb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-11_01,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 phishscore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 malwarescore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503110066 On 3/10/25 7:56 AM, Ziyue Zhang wrote: > From: Krishna chaitanya chundru > > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Signed-off-by: Krishna chaitanya chundru > Signed-off-by: Ziyue Zhang > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 142 +++++++++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index f4abfad474ea..282072084435 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -1001,6 +1001,148 @@ mmss_noc: interconnect@1740000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + pcie: pcie@1c08000 { Please set your tab size to 8 > + device_type = "pci"; > + compatible = "qcom,pcie-sm8550", "qcom,qcs615-pcie"; This is saying "this device is a SM8550 PCIe controller, which is compatible with QCS615's PCIe controller - should be the other way around.. Or according to the bindings you added in patch 1, this should just be "qcom,qcs615-pcie" > + reg = <0x0 0x01c08000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf1d>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x1000>, > + <0x0 0x40100000 0x0 0x100000>, > + <0x0 0x01c0b000 0x0 0x1000>; [...] > + phys = <&pcie_phy>; > + phy-names = "pciephy"; > + > + operating-points-v2 = <&pcie_opp_table>; > + > + status = "disabled"; > + pcie_opp_table: opp-table { Please add a newline before the subnode Konrad