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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id t21-20020ac24c15000000b004f858249931sm487188lfq.93.2023.07.06.19.34.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Jul 2023 19:34:04 -0700 (PDT) Message-ID: Date: Fri, 7 Jul 2023 05:34:04 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [Freedreno] [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Content-Language: en-GB To: Rob Clark , dri-devel@lists.freedesktop.org Cc: Konrad Dybcio , linux-arm-msm@vger.kernel.org, Rob Clark , freedreno@lists.freedesktop.org References: <20230706211045.204925-1-robdclark@gmail.com> <20230706211045.204925-7-robdclark@gmail.com> From: Dmitry Baryshkov In-Reply-To: <20230706211045.204925-7-robdclark@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 07/07/2023 00:10, Rob Clark wrote: > From: Rob Clark > > There are cases where there are differences due to SoC integration. > Such as cache-coherency support, and (in the next patch) e-fuse to > speedbin mappings. I have the feeling that we are trying to circumvent the way DT works. I'd suggest adding explicit SoC-compatible strings to Adreno bindings and then using of_device_id::data and then of_device_get_match_data(). > > Signed-off-by: Rob Clark > --- > drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- > drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + > 2 files changed, 31 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c > index 3c531da417b9..e62bc895a31f 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_device.c > +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { > .inactive_period = DRM_MSM_INACTIVE_PERIOD, > .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, > .init = a6xx_gpu_init, > + }, { > + .machine = "qcom,sm4350", > + .rev = ADRENO_REV(6, 1, 9, ANY_ID), > + .revn = 619, > + .fw = { > + [ADRENO_FW_SQE] = "a630_sqe.fw", > + [ADRENO_FW_GMU] = "a619_gmu.bin", > + }, > + .gmem = SZ_512K, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .init = a6xx_gpu_init, > + .zapfw = "a615_zap.mdt", > + .hwcg = a615_hwcg, > + }, { > + .machine = "qcom,sm6375", > + .rev = ADRENO_REV(6, 1, 9, ANY_ID), > + .revn = 619, > + .fw = { > + [ADRENO_FW_SQE] = "a630_sqe.fw", > + [ADRENO_FW_GMU] = "a619_gmu.bin", > + }, > + .gmem = SZ_512K, > + .inactive_period = DRM_MSM_INACTIVE_PERIOD, > + .init = a6xx_gpu_init, > + .zapfw = "a615_zap.mdt", > + .hwcg = a615_hwcg, > }, { > .rev = ADRENO_REV(6, 1, 9, ANY_ID), > .revn = 619, > @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev) > /* identify gpu: */ > for (i = 0; i < ARRAY_SIZE(gpulist); i++) { > const struct adreno_info *info = &gpulist[i]; > + if (info->machine && !of_machine_is_compatible(info->machine)) > + continue; > if (adreno_cmp_rev(info->rev, rev)) > return info; > } > @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > config.rev.minor, config.rev.patchid); > > priv->is_a2xx = config.rev.core == 2; > + priv->has_cached_coherent = > + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); > > gpu = info->init(drm); > if (IS_ERR(gpu)) { > @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) > if (ret) > return ret; > > - priv->has_cached_coherent = > - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && > - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); > - > return 0; > } > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > index e08d41337169..d5335b99c64c 100644 > --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h > @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h > extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; > > struct adreno_info { > + const char *machine; > struct adreno_rev rev; > uint32_t revn; > const char *fw[ADRENO_FW_MAX]; -- With best wishes Dmitry