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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 6/7] accel/qaic: Add config structs for supported cards Content-Language: en-US To: Jeffrey Hugo , , , , , CC: , , , , References: <20241213213340.2551697-1-quic_jhugo@quicinc.com> <20241213213340.2551697-7-quic_jhugo@quicinc.com> From: Lizhi Hou In-Reply-To: <20241213213340.2551697-7-quic_jhugo@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: None (SATLEXMB05.amd.com: lizhi.hou@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE9:EE_|DS0PR12MB8042:EE_ X-MS-Office365-Filtering-Correlation-Id: 1389bd9a-ca9c-4b1a-ef75-08dd1bd73577 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024|7416014|7053199007; X-Microsoft-Antispam-Message-Info: =?utf-8?B?Q29OZFZkdmt3dlpHNnZXU0lNNXNVVDg5V0xVWFkremlCWE5KZU5YLzNSd3BN?= =?utf-8?B?R20zRGZ5MHRncHBjeE82U1RNSHVUSnNaMWlkSW1xWUc0OE9iSWt6cDErSElr?= =?utf-8?B?OVdyaUlqQ0hucTZvdGNWZ2Rtd0hYcllBWnoxbE15VWZ0QkF1a0R3NTE5Q1hr?= =?utf-8?B?c3kwMnp1NXdSRzY0alVTeFh3MGlrYnJaSncvR01PRFF3TC9mSTZRRkE4eTN1?= =?utf-8?B?QzRqbi90SzZaczd2SzFMUE1maFBOMWZnNGVQazBzR1Q5L0ZIbHliQVlPYjJO?= =?utf-8?B?Tm9MOE8rdlh0ZlMvaFhFUC93YjNWT1hkNU9IUW1valowWWc2cHBjcGRJTDg2?= =?utf-8?B?dEQ5UGF1Z24waEoreFhXWVIyaWJmaksvZ25DeUhBTkRDRnZodk1zUWdDRE53?= =?utf-8?B?amxYQzhRUzJLYnlESllYKzJ0aHRMS1RyOU1Cb3U5dzdKREFFTklkWXFFQ0Rh?= =?utf-8?B?anJpa2diTEN2RkgxY1JWbXVTMkRXR1kvY2JQbFNGZ1FLcFFIZFZCZWdnUm80?= =?utf-8?B?TGw5ODRVZXdKYkE2LzRJTGZTN05meDJBOEJjOHI4ZU9keHI2c3dmSE1EUjdx?= =?utf-8?B?YnJJYWxUaHlBQnk0UjNlS0xNL2kzaDRlRktuR1lCNXdLb2cxN1ZYMS9LN2c4?= =?utf-8?B?bGhldmFHYWdJdXRONm9Kd1RuT09HdDZrSXhSUG8vRWZwbHBsTkpiSE1RaFM1?= =?utf-8?B?L2VFMzBTWUplWVdYc0w1OG9ydmtyUjJ3a04rbjhTU05TbHJSOHo0RlVDcy83?= =?utf-8?B?cFI4QTJtekJwaDgvMGs5ajlzWnhCZHZwb3Myc1VRWUJZL1I3N2U0VEpkeU5v?= =?utf-8?B?cHVVMjlxQnpDTWNlZDFPM3pVQ0ZYSUJzQyswMmR1WlhBTGkyN0VJSnIvMjZk?= =?utf-8?B?a3ZRV2VXK2JGLzJ0V1doVG5yd29wb1htM2FhY0JWckd6S21xU202eFZBUkQw?= =?utf-8?B?ZkEzZy9oYVBYb1JyWnVkUTg5OVkxMnYvM1U0OUg5Z2IwUEx0N3lSTkRZUEZt?= =?utf-8?B?Q2tQZ3FKMHVUeTg0Q0tDL1NlUzNJMXhXZHFHWlRweXRSQjlGU0F5LzVBci93?= =?utf-8?B?dUlPUEhtbmIxVVd1TGxmMDZPUitNaXR2SVZveG9hTG5Gb0dwdlZaRVlFRmIy?= =?utf-8?B?K1FJWUFETzNnYTlidmNDZ1ZVWElrUWtzZGtlaWtCTXptbUJuYkNxcy9tM29J?= =?utf-8?B?VFpDQzVXaUV2VGIwTzdYaE12bTZPdTJnUGMwc1BJNmJrTXVFUmswRXBRVFRx?= =?utf-8?B?eXNBQXp2VVZRTE5LME5RNFJDWTJsZUlWSC9CeFUvZ3VJMko0dmp3cmlUa2No?= =?utf-8?B?YTlac1VSK2hrelloT1YxL0RFUFU0anZmRmFKdFJtVnBTVHJWdTlhVGYrTmRG?= =?utf-8?B?L2VxS3llZVMza1Y4WjEwR1ZMYkdvcWhJTWdjOVJkWFpxVWNBMDlDY1ZxaGY5?= =?utf-8?B?b0llSzU2Z1BBU3lTN3ZLTVFidDU3SWZ4bVpCRXB4SGhjdXhpSU1FNk9ObjFB?= =?utf-8?B?eDRaWnVFdlQxYmVqNnljaStoZSs1MDhyR3Q2OTVxOWJXRHFYN1g4N3lXS1Yw?= =?utf-8?B?N3ZRUCs5UUxmTkNzdGJSU2E1TUx0ekRmU2tRckNkYTlzcGwrbmZla2toRm1F?= =?utf-8?B?bWw3c2xZb21YVGdndWFlcTAvMDdlTWRseXZGa2ZHUExhdlAzWVY1YVVzaG0w?= =?utf-8?B?eHZnT2VTeGNxeEhoZVBpRzRmUFd5a0d4Q0IwOUx5TENISmdWS0hic1JmYWth?= =?utf-8?B?SW0zamlna2ZhUnBtRHpVbEtWUDVZRjNDQ1ZLcWhqV3Q5Z1BscFRUd1Q0dUVl?= =?utf-8?B?YUx4RlcxZnBHMEsyTmU1V2d6MFJSRjVjRW44M2Ixc2JhdWcvNDNoSnJyMklt?= =?utf-8?B?MGt4dXkxYXo0MmxQZ1Y2Y3NIK3NsSnJrUmVFRlR4ZzNZcUtVblpkSDEza1I0?= =?utf-8?Q?ToM+35g3j+wFt4WBKa1eeIe2W/OzzDiT?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024)(7416014)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Dec 2024 00:35:28.3887 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1389bd9a-ca9c-4b1a-ef75-08dd1bd73577 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8042 On 12/13/24 13:33, Jeffrey Hugo wrote: > As the number of cards supported by the driver grows, their > configurations will differ. The driver needs to become more dynamic > to support these configurations. Currently, each card may differ in > the exposed BARs, the regions they map to, and the family. > > Create config structs for each card, and let the driver configure the > qaic_device struct based on the configurations passed to the driver. > > Co-developed-by: Youssef Samir > Signed-off-by: Youssef Samir > Signed-off-by: Jeffrey Hugo > --- > drivers/accel/qaic/qaic.h | 13 +++-- > drivers/accel/qaic/qaic_drv.c | 76 ++++++++++++++++++++---------- > drivers/accel/qaic/qaic_timesync.c | 2 +- > 3 files changed, 61 insertions(+), 30 deletions(-) > > diff --git a/drivers/accel/qaic/qaic.h b/drivers/accel/qaic/qaic.h > index 02561b6cecc6..cf97fd9a7e70 100644 > --- a/drivers/accel/qaic/qaic.h > +++ b/drivers/accel/qaic/qaic.h > @@ -32,6 +32,11 @@ > #define to_accel_kdev(qddev) (to_drm(qddev)->accel->kdev) /* Return Linux device of accel node */ > #define to_qaic_device(dev) (to_qaic_drm_device((dev))->qdev) > > +enum aic_families { > + FAMILY_AIC100, > + FAMILY_MAX, > +}; > + > enum __packed dev_states { > /* Device is offline or will be very soon */ > QAIC_OFFLINE, > @@ -113,10 +118,10 @@ struct qaic_device { > struct pci_dev *pdev; > /* Req. ID of request that will be queued next in MHI control device */ > u32 next_seq_num; > - /* Base address of bar 0 */ > - void __iomem *bar_0; > - /* Base address of bar 2 */ > - void __iomem *bar_2; > + /* Base address of the MHI bar */ > + void __iomem *bar_mhi; > + /* Base address of the DBCs bar */ > + void __iomem *bar_dbc; > /* Controller structure for MHI devices */ > struct mhi_controller *mhi_cntrl; > /* MHI control channel device */ > diff --git a/drivers/accel/qaic/qaic_drv.c b/drivers/accel/qaic/qaic_drv.c > index 00fa07aebacd..4e63e475b389 100644 > --- a/drivers/accel/qaic/qaic_drv.c > +++ b/drivers/accel/qaic/qaic_drv.c > @@ -34,13 +34,38 @@ > > MODULE_IMPORT_NS("DMA_BUF"); > > -#define PCI_DEV_AIC080 0xa080 > -#define PCI_DEV_AIC100 0xa100 > +#define PCI_DEVICE_ID_QCOM_AIC080 0xa080 > +#define PCI_DEVICE_ID_QCOM_AIC100 0xa100 > #define QAIC_NAME "qaic" > #define QAIC_DESC "Qualcomm Cloud AI Accelerators" > #define CNTL_MAJOR 5 > #define CNTL_MINOR 0 > > +struct qaic_device_config { > + /* Indicates the AIC family the device belongs to */ > + int family; > + /* A bitmask representing the available BARs */ > + int bar_mask; > + /* An index value used to identify the MHI controller BAR */ > + unsigned int mhi_bar_idx; > + /* An index value used to identify the DBCs BAR */ > + unsigned int dbc_bar_idx; > +}; > + > +static const struct qaic_device_config aic080_config = { > + .family = FAMILY_AIC100, > + .bar_mask = BIT(0) | BIT(2) | BIT(4), > + .mhi_bar_idx = 0, > + .dbc_bar_idx = 2, > +}; > + > +static const struct qaic_device_config aic100_config = { > + .family = FAMILY_AIC100, > + .bar_mask = BIT(0) | BIT(2) | BIT(4), > + .mhi_bar_idx = 0, > + .dbc_bar_idx = 2, > +}; > + > bool datapath_polling; > module_param(datapath_polling, bool, 0400); > MODULE_PARM_DESC(datapath_polling, "Operate the datapath in polling mode"); > @@ -352,7 +377,8 @@ void qaic_dev_reset_clean_local_state(struct qaic_device *qdev) > release_dbc(qdev, i); > } > > -static struct qaic_device *create_qdev(struct pci_dev *pdev, const struct pci_device_id *id) > +static struct qaic_device *create_qdev(struct pci_dev *pdev, > + const struct qaic_device_config *config) > { > struct device *dev = &pdev->dev; > struct qaic_drm_device *qddev; > @@ -365,12 +391,10 @@ static struct qaic_device *create_qdev(struct pci_dev *pdev, const struct pci_de > return NULL; > > qdev->dev_state = QAIC_OFFLINE; > - if (id->device == PCI_DEV_AIC080 || id->device == PCI_DEV_AIC100) { > - qdev->num_dbc = 16; > - qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL); > - if (!qdev->dbc) > - return NULL; > - } > + qdev->num_dbc = 16; Is it better to put num_dbc in qaic_device_config? Thanks, Lizhi > + qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL); > + if (!qdev->dbc) > + return NULL; > > qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm); > if (IS_ERR(qddev)) > @@ -426,7 +450,8 @@ static struct qaic_device *create_qdev(struct pci_dev *pdev, const struct pci_de > return qdev; > } > > -static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev) > +static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev, > + const struct qaic_device_config *config) > { > int bars; > int ret; > @@ -434,9 +459,9 @@ static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev) > bars = pci_select_bars(pdev, IORESOURCE_MEM) & 0x3f; > > /* make sure the device has the expected BARs */ > - if (bars != (BIT(0) | BIT(2) | BIT(4))) { > - pci_dbg(pdev, "%s: expected BARs 0, 2, and 4 not found in device. Found 0x%x\n", > - __func__, bars); > + if (bars != config->bar_mask) { > + pci_dbg(pdev, "%s: expected BARs %#x not found in device. Found %#x\n", > + __func__, config->bar_mask, bars); > return -EINVAL; > } > > @@ -449,13 +474,13 @@ static int init_pci(struct qaic_device *qdev, struct pci_dev *pdev) > return ret; > dma_set_max_seg_size(&pdev->dev, UINT_MAX); > > - qdev->bar_0 = devm_ioremap_resource(&pdev->dev, &pdev->resource[0]); > - if (IS_ERR(qdev->bar_0)) > - return PTR_ERR(qdev->bar_0); > + qdev->bar_mhi = devm_ioremap_resource(&pdev->dev, &pdev->resource[config->mhi_bar_idx]); > + if (IS_ERR(qdev->bar_mhi)) > + return PTR_ERR(qdev->bar_mhi); > > - qdev->bar_2 = devm_ioremap_resource(&pdev->dev, &pdev->resource[2]); > - if (IS_ERR(qdev->bar_2)) > - return PTR_ERR(qdev->bar_2); > + qdev->bar_dbc = devm_ioremap_resource(&pdev->dev, &pdev->resource[config->dbc_bar_idx]); > + if (IS_ERR(qdev->bar_dbc)) > + return PTR_ERR(qdev->bar_dbc); > > /* Managed release since we use pcim_enable_device above */ > pci_set_master(pdev); > @@ -517,21 +542,22 @@ static int init_msi(struct qaic_device *qdev, struct pci_dev *pdev) > > static int qaic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > + struct qaic_device_config *config = (struct qaic_device_config *)id->driver_data; > struct qaic_device *qdev; > int mhi_irq; > int ret; > int i; > > - qdev = create_qdev(pdev, id); > + qdev = create_qdev(pdev, config); > if (!qdev) > return -ENOMEM; > > - ret = init_pci(qdev, pdev); > + ret = init_pci(qdev, pdev, config); > if (ret) > return ret; > > for (i = 0; i < qdev->num_dbc; ++i) > - qdev->dbc[i].dbc_base = qdev->bar_2 + QAIC_DBC_OFF(i); > + qdev->dbc[i].dbc_base = qdev->bar_dbc + QAIC_DBC_OFF(i); > > mhi_irq = init_msi(qdev, pdev); > if (mhi_irq < 0) > @@ -541,7 +567,7 @@ static int qaic_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > if (ret) > return ret; > > - qdev->mhi_cntrl = qaic_mhi_register_controller(pdev, qdev->bar_0, mhi_irq, > + qdev->mhi_cntrl = qaic_mhi_register_controller(pdev, qdev->bar_mhi, mhi_irq, > qdev->single_msi); > if (IS_ERR(qdev->mhi_cntrl)) { > ret = PTR_ERR(qdev->mhi_cntrl); > @@ -609,8 +635,8 @@ static struct mhi_driver qaic_mhi_driver = { > }; > > static const struct pci_device_id qaic_ids[] = { > - { PCI_DEVICE(PCI_VENDOR_ID_QCOM, PCI_DEV_AIC080), }, > - { PCI_DEVICE(PCI_VENDOR_ID_QCOM, PCI_DEV_AIC100), }, > + { PCI_DEVICE_DATA(QCOM, AIC080, (kernel_ulong_t)&aic080_config), }, > + { PCI_DEVICE_DATA(QCOM, AIC100, (kernel_ulong_t)&aic100_config), }, > { } > }; > MODULE_DEVICE_TABLE(pci, qaic_ids); > diff --git a/drivers/accel/qaic/qaic_timesync.c b/drivers/accel/qaic/qaic_timesync.c > index 301f4462d51b..2473c66309d4 100644 > --- a/drivers/accel/qaic/qaic_timesync.c > +++ b/drivers/accel/qaic/qaic_timesync.c > @@ -201,7 +201,7 @@ static int qaic_timesync_probe(struct mhi_device *mhi_dev, const struct mhi_devi > goto free_sync_msg; > > /* Qtimer register pointer */ > - mqtsdev->qtimer_addr = qdev->bar_0 + QTIMER_REG_OFFSET; > + mqtsdev->qtimer_addr = qdev->bar_mhi + QTIMER_REG_OFFSET; > timer_setup(timer, qaic_timesync_timer, 0); > timer->expires = jiffies + msecs_to_jiffies(timesync_delay_ms); > add_timer(timer);