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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acaa1cb3d8fsm491976666b.106.2025.04.11.12.26.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Apr 2025 12:26:34 -0700 (PDT) Message-ID: Date: Fri, 11 Apr 2025 21:26:32 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] arm64: dts: qcom: sm6350: Add video clock controller To: Jagadeesh Kona , Konrad Dybcio , Luca Weiss , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250324-sm6350-videocc-v2-0-cc22386433f4@fairphone.com> <20250324-sm6350-videocc-v2-4-cc22386433f4@fairphone.com> <1c09fee5-9626-4540-83fb-6d90db2ce595@oss.qualcomm.com> <9eb6dfd7-2716-4150-9392-98e26892d82d@quicinc.com> <69fba227-ed47-4004-9451-777ca19b687f@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <69fba227-ed47-4004-9451-777ca19b687f@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: UzrGY_XQKXBNCWofA1UiuB1F5EWZxeaY X-Authority-Analysis: v=2.4 cv=T7OMT+KQ c=1 sm=1 tr=0 ts=67f96cec cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=6H0WHjuAAAAA:8 a=_xYJqbmhMe1K5No2dSMA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=TjNXssC_j7lpFel5tvFf:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-ORIG-GUID: UzrGY_XQKXBNCWofA1UiuB1F5EWZxeaY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_07,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 mlxscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110123 On 4/11/25 1:37 PM, Jagadeesh Kona wrote: > > > On 4/11/2025 2:42 PM, Konrad Dybcio wrote: >> On 4/11/25 9:15 AM, Jagadeesh Kona wrote: >>> >>> >>> On 4/1/2025 10:03 PM, Konrad Dybcio wrote: >>>> On 3/24/25 9:41 AM, Luca Weiss wrote: >>>>> Add a node for the videocc found on the SM6350 SoC. >>>>> >>>>> Signed-off-by: Luca Weiss >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 14 ++++++++++++++ >>>>> 1 file changed, 14 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> index 42f9d16c2fa6da66a8bb524a33c2687a1e4b40e0..4498d6dfd61a7e30a050a8654d54dae2d06c220c 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> @@ -1952,6 +1952,20 @@ usb_1_dwc3_ss_out: endpoint { >>>>> }; >>>>> }; >>>>> >>>>> + videocc: clock-controller@aaf0000 { >>>>> + compatible = "qcom,sm6350-videocc"; >>>>> + reg = <0x0 0x0aaf0000 0x0 0x10000>; >>>>> + clocks = <&gcc GCC_VIDEO_AHB_CLK>, >>>>> + <&rpmhcc RPMH_CXO_CLK>, >>>>> + <&sleep_clk>; >>>>> + clock-names = "iface", >>>>> + "bi_tcxo", >>>>> + "sleep_clk"; >>>>> + #clock-cells = <1>; >>>>> + #reset-cells = <1>; >>>>> + #power-domain-cells = <1>; >>>>> + }; >>>> >>>> You'll probably want to hook up some additional power domains here, see >>>> >>>> https://lore.kernel.org/linux-arm-msm/20250327-videocc-pll-multi-pd-voting-v3-0-895fafd62627@quicinc.com/ >>>> >>> >>> On SM6350, videocc doesn't need multiple power domains at HW level, it is only on CX rail which would be ON >>> when system is active, hence power-domains are not mandatory here. >> >> 6350 doesn't have either MMCX nor a split MX - shouldn't both normal >> CX and MX be in there? >> > > All clocks & GDSC's of SM6350 videocc are only on CX rail, so it requires only CX power domain. But when HLOS > is active, CX rail will be ON and operate at a level above retention, which is sufficient for videocc to operate. > Hence clock driver don't need to explicitly vote on CX rail. > > The same is not true for other rails like MMCX and Split MX(MXC), hence clock drivers had to explicitly vote on > those rails. I'm worried about MX being undervolted for higher OPPs Konrad