[PATCH 0/3] Add QFPROM support for few IPQ SoCs

[PATCH 0/3] Add QFPROM support for few IPQ SoCs

[Kathiravan T]

Like any other SOCs, Qualcomm's IPQ SOCs also have an efuse region which
exposes the HW quirks like CPU Freq limit and so on. This series add the
basic support for the efuse. Feature specific fuses will be added along
with the feature set.

Kathiravan T (4):
  dt-bindings: nvmem: qfprom: add compatible for few IPQ SoCs
  arm64: dts: qcom: ipq5332: add QFPROM node
  arm64: dts: qcom: ipq6018: add QFPROM node
  arm64: dts: qcom: ipq9574: add QFPROM node

 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 3 +++
 arch/arm64/boot/dts/qcom/ipq5332.dtsi                    | 7 +++++++
 arch/arm64/boot/dts/qcom/ipq6018.dtsi                    | 7 +++++++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi                    | 7 +++++++
 4 files changed, 24 insertions(+)

-- 
2.17.1

[PATCH 1/4] dt-bindings: nvmem: qfprom: add compatible for few IPQ SoCs

[Kathiravan T]

Add the QFPROM compatible for IPQ5332, IPQ6018 and IPQ9574

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
index 8d8503dd934b..076566ef9cc8 100644
--- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
+++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
@@ -18,8 +18,11 @@ properties:
       - enum:
           - qcom,apq8064-qfprom
           - qcom,apq8084-qfprom
+          - qcom,ipq5332-qfprom
+          - qcom,ipq6018-qfprom
           - qcom,ipq8064-qfprom
           - qcom,ipq8074-qfprom
+          - qcom,ipq9574-qfprom
           - qcom,msm8916-qfprom
           - qcom,msm8974-qfprom
           - qcom,msm8976-qfprom
-- 
2.17.1

[PATCH 2/4] arm64: dts: qcom: ipq5332: add QFPROM node

[Kathiravan T]

IPQ5332 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index af4d97143bcf..c2d6cc65a323 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -135,6 +135,13 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
+		qfprom: efuse@a4000 {
+			compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
+			reg = <0x000a4000 0x721>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		rng: rng@e3000 {
 			compatible = "qcom,prng-ee";
 			reg = <0x000e3000 0x1000>;
-- 
2.17.1

[PATCH 3/4] arm64: dts: qcom: ipq6018: add QFPROM node

[Kathiravan T]

IPQ6018 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index f531797f2619..856879fd0207 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -206,6 +206,13 @@
 		dma-ranges;
 		compatible = "simple-bus";
 
+		qfprom: efuse@a4000 {
+			compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
+			reg = <0x0 0x000a4000 0x0 0x2000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		qusb_phy_1: qusb@59000 {
 			compatible = "qcom,ipq6018-qusb2-phy";
 			reg = <0x0 0x00059000 0x0 0x180>;
-- 
2.17.1

[PATCH 4/4] arm64: dts: qcom: ipq9574: add QFPROM node

[Kathiravan T]

IPQ9574 has efuse region to determine the various HW quirks. Lets
add the initial support and the individual fuses will be added as they
are required.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 1a2c813ffd43..715fe51ff567 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -117,6 +117,13 @@
 		#size-cells = <1>;
 		ranges = <0 0 0 0xffffffff>;
 
+		qfprom: efuse@a4000 {
+			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
+			reg = <0x000a4000 0x5a1>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq9574-tlmm";
 			reg = <0x01000000 0x300000>;
-- 
2.17.1

Re: [PATCH 2/4] arm64: dts: qcom: ipq5332: add QFPROM node

[Konrad Dybcio]

On 26.05.2023 09:04, Kathiravan T wrote:
> IPQ5332 has efuse region to determine the various HW quirks. Lets
> add the initial support and the individual fuses will be added as they
> are required.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> index af4d97143bcf..c2d6cc65a323 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
> @@ -135,6 +135,13 @@
>  		#size-cells = <1>;
>  		ranges = <0 0 0 0xffffffff>;
>  
> +		qfprom: efuse@a4000 {
> +			compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
> +			reg = <0x000a4000 0x721>;
That's an odd size. Are you sure this is how long the corrected region is?

Konrad
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +		};
> +
>  		rng: rng@e3000 {
>  			compatible = "qcom,prng-ee";
>  			reg = <0x000e3000 0x1000>;

Re: [PATCH 4/4] arm64: dts: qcom: ipq9574: add QFPROM node

[Konrad Dybcio]

On 26.05.2023 09:04, Kathiravan T wrote:
> IPQ9574 has efuse region to determine the various HW quirks. Lets
> add the initial support and the individual fuses will be added as they
> are required.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 1a2c813ffd43..715fe51ff567 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -117,6 +117,13 @@
>  		#size-cells = <1>;
>  		ranges = <0 0 0 0xffffffff>;
>  
> +		qfprom: efuse@a4000 {
> +			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
> +			reg = <0x000a4000 0x5a1>;
That's an odd size. Are you sure this is how long the corrected region is?

Konrad
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +		};
> +
>  		tlmm: pinctrl@1000000 {
>  			compatible = "qcom,ipq9574-tlmm";
>  			reg = <0x01000000 0x300000>;

Re: [PATCH 3/4] arm64: dts: qcom: ipq6018: add QFPROM node

[Konrad Dybcio]

On 26.05.2023 09:04, Kathiravan T wrote:
> IPQ6018 has efuse region to determine the various HW quirks. Lets
> add the initial support and the individual fuses will be added as they
> are required.
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index f531797f2619..856879fd0207 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -206,6 +206,13 @@
>  		dma-ranges;
>  		compatible = "simple-bus";
>  
> +		qfprom: efuse@a4000 {
This should be a bit lower down (0xa4000 > 0x59000)

Konrad
> +			compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
> +			reg = <0x0 0x000a4000 0x0 0x2000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +		};
> +
>  		qusb_phy_1: qusb@59000 {
>  			compatible = "qcom,ipq6018-qusb2-phy";
>  			reg = <0x0 0x00059000 0x0 0x180>;

Re: [PATCH 3/4] arm64: dts: qcom: ipq6018: add QFPROM node

[Kathiravan T]

On 5/26/2023 2:54 PM, Konrad Dybcio wrote:
>
> On 26.05.2023 09:04, Kathiravan T wrote:
>> IPQ6018 has efuse region to determine the various HW quirks. Lets
>> add the initial support and the individual fuses will be added as they
>> are required.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> index f531797f2619..856879fd0207 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
>> @@ -206,6 +206,13 @@
>>   		dma-ranges;
>>   		compatible = "simple-bus";
>>   
>> +		qfprom: efuse@a4000 {
> This should be a bit lower down (0xa4000 > 0x59000)


Sorry, missed this. Will address in V2.


>
> Konrad
>> +			compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
>> +			reg = <0x0 0x000a4000 0x0 0x2000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +		};
>> +
>>   		qusb_phy_1: qusb@59000 {
>>   			compatible = "qcom,ipq6018-qusb2-phy";
>>   			reg = <0x0 0x00059000 0x0 0x180>;

Re: [PATCH 4/4] arm64: dts: qcom: ipq9574: add QFPROM node

[Kathiravan T]

On 5/26/2023 2:49 PM, Konrad Dybcio wrote:
>
> On 26.05.2023 09:04, Kathiravan T wrote:
>> IPQ9574 has efuse region to determine the various HW quirks. Lets
>> add the initial support and the individual fuses will be added as they
>> are required.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 1a2c813ffd43..715fe51ff567 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -117,6 +117,13 @@
>>   		#size-cells = <1>;
>>   		ranges = <0 0 0 0xffffffff>;
>>   
>> +		qfprom: efuse@a4000 {
>> +			compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
>> +			reg = <0x000a4000 0x5a1>;
> That's an odd size. Are you sure this is how long the corrected region is?


Yes, As per the HW document, this is the size.


>
> Konrad
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +		};
>> +
>>   		tlmm: pinctrl@1000000 {
>>   			compatible = "qcom,ipq9574-tlmm";
>>   			reg = <0x01000000 0x300000>;

Re: [PATCH 2/4] arm64: dts: qcom: ipq5332: add QFPROM node

[Kathiravan T]

On 5/26/2023 2:49 PM, Konrad Dybcio wrote:
>
> On 26.05.2023 09:04, Kathiravan T wrote:
>> IPQ5332 has efuse region to determine the various HW quirks. Lets
>> add the initial support and the individual fuses will be added as they
>> are required.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> index af4d97143bcf..c2d6cc65a323 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>> @@ -135,6 +135,13 @@
>>   		#size-cells = <1>;
>>   		ranges = <0 0 0 0xffffffff>;
>>   
>> +		qfprom: efuse@a4000 {
>> +			compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
>> +			reg = <0x000a4000 0x721>;
> That's an odd size. Are you sure this is how long the corrected region is?


Yes, As per the HW document, this is the size.


>
> Konrad
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +		};
>> +
>>   		rng: rng@e3000 {
>>   			compatible = "qcom,prng-ee";
>>   			reg = <0x000e3000 0x1000>;

Re: [PATCH 2/4] arm64: dts: qcom: ipq5332: add QFPROM node

[Konrad Dybcio]

On 26.05.2023 12:24, Kathiravan T wrote:
> 
> On 5/26/2023 2:49 PM, Konrad Dybcio wrote:
>>
>> On 26.05.2023 09:04, Kathiravan T wrote:
>>> IPQ5332 has efuse region to determine the various HW quirks. Lets
>>> add the initial support and the individual fuses will be added as they
>>> are required.
>>>
>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/ipq5332.dtsi | 7 +++++++
>>>   1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>> index af4d97143bcf..c2d6cc65a323 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
>>> @@ -135,6 +135,13 @@
>>>           #size-cells = <1>;
>>>           ranges = <0 0 0 0xffffffff>;
>>>   +        qfprom: efuse@a4000 {
>>> +            compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
>>> +            reg = <0x000a4000 0x721>;
>> That's an odd size. Are you sure this is how long the corrected region is?
> 
> 
> Yes, As per the HW document, this is the size.
OK thanks for confirming

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
> 
> 
>>
>> Konrad
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +        };
>>> +
>>>           rng: rng@e3000 {
>>>               compatible = "qcom,prng-ee";
>>>               reg = <0x000e3000 0x1000>;

Re: [PATCH 4/4] arm64: dts: qcom: ipq9574: add QFPROM node

[Konrad Dybcio]

On 26.05.2023 12:24, Kathiravan T wrote:
> 
> On 5/26/2023 2:49 PM, Konrad Dybcio wrote:
>>
>> On 26.05.2023 09:04, Kathiravan T wrote:
>>> IPQ9574 has efuse region to determine the various HW quirks. Lets
>>> add the initial support and the individual fuses will be added as they
>>> are required.
>>>
>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi | 7 +++++++
>>>   1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> index 1a2c813ffd43..715fe51ff567 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> @@ -117,6 +117,13 @@
>>>           #size-cells = <1>;
>>>           ranges = <0 0 0 0xffffffff>;
>>>   +        qfprom: efuse@a4000 {
>>> +            compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
>>> +            reg = <0x000a4000 0x5a1>;
>> That's an odd size. Are you sure this is how long the corrected region is?
> 
> 
> Yes, As per the HW document, this is the size.
Thanks for confirming

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
> 
> 
>>
>> Konrad
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +        };
>>> +
>>>           tlmm: pinctrl@1000000 {
>>>               compatible = "qcom,ipq9574-tlmm";
>>>               reg = <0x01000000 0x300000>;

Re: [PATCH 1/4] dt-bindings: nvmem: qfprom: add compatible for few IPQ SoCs

[Conor Dooley]

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On Fri, May 26, 2023 at 12:34:18PM +0530, Kathiravan T wrote:
> Add the QFPROM compatible for IPQ5332, IPQ6018 and IPQ9574
> 
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

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