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Tue, 30 Mar 2021 00:01:12 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: abhinavk) by smtp.codeaurora.org (Postfix) with ESMTPSA id 8FFACC433ED; Tue, 30 Mar 2021 00:01:11 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Mon, 29 Mar 2021 17:01:11 -0700 From: abhinavk@codeaurora.org To: Dmitry Baryshkov Cc: Rob Clark , Sean Paul , Jonathan Marek , Michael Turquette , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Daniel Vetter , freedreno@lists.freedesktop.org, linux-clk@vger.kernel.org Subject: Re: [Freedreno] [PATCH v3 15/25] drm/msm/dsi: drop vco_delay setting from 7nm, 10nm, 14nm drivers In-Reply-To: <20210327110305.3289784-16-dmitry.baryshkov@linaro.org> References: <20210327110305.3289784-1-dmitry.baryshkov@linaro.org> <20210327110305.3289784-16-dmitry.baryshkov@linaro.org> Message-ID: X-Sender: abhinavk@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2021-03-27 04:02, Dmitry Baryshkov wrote: > These drivers do not use vco_delay variable, so drop it from all of > them. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- > 3 files changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > index e0df12a841b2..bfb96d87d1d7 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c > @@ -99,7 +99,6 @@ struct dsi_pll_10nm { > /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ > spinlock_t postdiv_lock; > > - int vco_delay; > struct dsi_pll_config pll_configuration; > struct dsi_pll_regs reg_setup; > > @@ -771,8 +770,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy > *phy) > pll = &pll_10nm->base; > pll->cfg = phy->cfg; > > - pll_10nm->vco_delay = 1; > - > ret = pll_10nm_register(pll_10nm, phy->provided_clocks->hws); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 7fe7c8348b42..434d02ffa7fe 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -122,8 +122,6 @@ struct dsi_pll_14nm { > void __iomem *phy_cmn_mmio; > void __iomem *mmio; > > - int vco_delay; > - > struct dsi_pll_input in; > struct dsi_pll_output out; > > @@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy > *phy) > pll = &pll_14nm->base; > pll->cfg = phy->cfg; > > - pll_14nm->vco_delay = 1; > - > ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > index e6c8040e1bd3..f760904efac9 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c > @@ -99,7 +99,6 @@ struct dsi_pll_7nm { > /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ > spinlock_t postdiv_lock; > > - int vco_delay; > struct dsi_pll_config pll_configuration; > struct dsi_pll_regs reg_setup; > > @@ -796,8 +795,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy > *phy) > pll = &pll_7nm->base; > pll->cfg = phy->cfg; > > - pll_7nm->vco_delay = 1; > - > ret = pll_7nm_register(pll_7nm, phy->provided_clocks->hws); > if (ret) { > DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);