From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Dwivedi, Avaneesh Kumar (avani)" Subject: Re: [RESEND PATCH v4 5/7] remoteproc: qcom: Modify reset sequence for hexagon to support v56 1.5.0 Date: Wed, 14 Dec 2016 01:15:16 +0530 Message-ID: References: <1479981638-32069-1-git-send-email-akdwived@codeaurora.org> <1479981638-32069-6-git-send-email-akdwived@codeaurora.org> <20161209043510.GS30492@tuxbot> <0f3dbcbb-4ed5-dac8-a9c7-a22d597f4be5@codeaurora.org> <20161213180924.GG3439@tuxbot> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from smtp.codeaurora.org ([198.145.29.96]:57784 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933054AbcLMTpY (ORCPT ); Tue, 13 Dec 2016 14:45:24 -0500 In-Reply-To: <20161213180924.GG3439@tuxbot> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Bjorn Andersson Cc: sboyd@codeaurora.org, agross@codeaurora.org, linux-arm-msm@vger.kernel.org On 12/13/2016 11:39 PM, Bjorn Andersson wrote: > On Mon 12 Dec 04:45 PST 2016, Dwivedi, Avaneesh Kumar (avani) wrote: >> On 12/9/2016 10:05 AM, Bjorn Andersson wrote: >>> On Thu 24 Nov 02:00 PST 2016, Avaneesh Kumar Dwivedi wrote: > [..] >>>> + >>>> + /* Turn on L1, L2, ETB and JU memories 1 at a time */ >>>> + val = readl_relaxed(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); >>>> + for (i = 19; i >= 0; i--) { >>>> + val |= BIT(i); >>>> + writel_relaxed(val, qproc->reg_base + >>>> + QDSP6SS_MEM_PWR_CTL); >>>> + /* >>>> + * Wait for 1us for both memory peripheral and >>>> + * data array to turn on. >>>> + */ >>>> + mb(); >>> mb() ensures that your writes are ordered, it does not ensure that the >>> write is done before the sleep. What is the actual requirement here? >> As in comment, order of turning need to be serialized so this memory >> barrier. >> Do u think its not required? > The problem is that mb() don't actually wait for the write to finish, it > simply makes sure that any subsequent writes will come after this one. mb() is for below comment /* Turn on L1, L2, ETB and JU memories 1 at a time */ While delay corresponding to /* + * Wait for 1us for both memory peripheral and + * data array to turn on. + */ > > If we want to make sure the write actually hits the hardware before the > delay we should read the register back after the write - as that would > stall execution until the write is available. > > Either way, using the non-_relaxed version of writel() will be > equivalent to what you have now. Do you mean if writel is used , udelay() should be removed? i understand writel will not return before register write operation is actually done. udelay() is to give enough time so that after writel , there is some time available to turn on mem peripheral and data array. > >>>> + udelay(1); >>>> + } > Regards, > Bjorn -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.