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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id p16-20020a05651211f000b004fbab80ecefsm44941lfs.145.2023.07.10.13.54.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Jul 2023 13:54:03 -0700 (PDT) Message-ID: Date: Mon, 10 Jul 2023 23:54:02 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [Freedreno] [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Content-Language: en-GB To: Rob Clark Cc: dri-devel@lists.freedesktop.org, Konrad Dybcio , linux-arm-msm@vger.kernel.org, Rob Clark , freedreno@lists.freedesktop.org References: <20230706211045.204925-1-robdclark@gmail.com> <20230706211045.204925-8-robdclark@gmail.com> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 10/07/2023 22:56, Rob Clark wrote: > On Thu, Jul 6, 2023 at 7:54 PM Dmitry Baryshkov > wrote: >> >> On 07/07/2023 00:10, Rob Clark wrote: >>> From: Rob Clark >>> >>> This simplifies the code. >>> >>> Signed-off-by: Rob Clark >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++------------------- >>> drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++ >>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 25 +++ >>> 3 files changed, 92 insertions(+), 155 deletions(-) >> >> >> Interesting hack, I'd say. >> >> Reviewed-by: Dmitry Baryshkov >> >> Minor nit below. >> >>> >> >>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>> index d5335b99c64c..994ac26ce731 100644 >>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h >>> @@ -72,8 +72,33 @@ struct adreno_info { >>> u32 inactive_period; >>> const struct adreno_reglist *hwcg; >>> u64 address_space_size; >>> + /** >>> + * @speedbins: Optional table of fuse to speedbin mappings >>> + * >>> + * Consists of pairs of fuse, index mappings, terminated with >>> + * UINT_MAX sentinal. >>> + */ >>> + uint32_t *speedbins; >> >> Would it be better to explicitly list this as pairs of uint32_t? And >> then use braces in ADRENO_SPEEDBIN initialisation. > > It would mean the sentinel would take 8 bytes instead of 4.. maybe > that is over-thinking it, but it was the reason I just stuck with a > flat table Guessed so. But we are wasting so much memory already... I think that the paired structure would better reflect the data - it's not a flat list, but a list of nvmem <-> speedbin pairs. > > BR, > -R > >>> }; >>> >>> +/* >>> + * Helper to build a speedbin table, ie. the table: >>> + * fuse | speedbin >>> + * -----+--------- >>> + * 0 | 0 >>> + * 169 | 1 >>> + * 174 | 2 >>> + * >>> + * would be declared as: >>> + * >>> + * .speedbins = ADRENO_SPEEDBINS( >>> + * 0, 0, >>> + * 169, 1, >>> + * 174, 2 >>> + * ), >>> + */ >>> +#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX } >>> + >>> const struct adreno_info *adreno_info(struct adreno_rev rev); >>> >>> struct adreno_gpu { >> >> -- >> With best wishes >> Dmitry >> -- With best wishes Dmitry