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Fri, 26 Jun 2026 09:02:18 -0700 (PDT) X-Received: by 2002:a05:6102:cc9:b0:71e:1551:183a with SMTP id ada2fe7eead31-7343761785amr1584063137.8.1782489737454; Fri, 26 Jun 2026 09:02:17 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-697f46e15besm3077659a12.15.2026.06.26.09.02.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Jun 2026 09:02:15 -0700 (PDT) Message-ID: Date: Fri, 26 Jun 2026 18:02:12 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/3] arm64: dts: qcom: kodiak: Enable 4-lane DP via QMP Combo PHY To: Doug Anderson Cc: Bjorn Andersson , Mahadevan P , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahadevan P , Stephen Boyd References: <20260429-kodiak_v2-v2-0-c3a703cc30eb@oss.qualcomm.com> <84ed2c32-16d0-4c29-a06a-9242eeb8e86e@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI2MDEzMiBTYWx0ZWRfX2OsQASgv4Nf/ sIhYe3jt2a83uZzvmQEG22sPnInHk8JjKSemmoznqItFCcZ5Dw1n37kTkl31SHxzri1OvoFeGx3 MFsgNt0vnYkJBdJNujoH8GbiWrdxeCP/t6c4PRqVx3nBwvLQHxW5kzqpZdYM/iPPKxhygYSu/HL UMVP4+kWMnQW/vlGMgGiQhn/Nia6HL2yO8qydBwxE3IGsIjs8Ictdh3kX45meqjby2erqtiasfH 9lBMJae4o8RZ2Eq7lVFDgBKnrAl+M6rA8D2fBkpOsfVx03EhgUALMpC4xqln31ZXyF5Q8cJBceJ 2pnCe6qnYl6w1jPawyNaBh51wPGHQ/TYjkybM2J2szU2uAIWGev0k4DH3UROTrL1JMs+HcCMysg R+e9WNgRzqTbTi7Ly76eBxMm3VFFen+vQQaYSnlCdhLQrJUrZE8/jSIN2mhuW2A1hd6Xyg5MhqI mcQFXBxv1rKErbeB8OA== X-Proofpoint-ORIG-GUID: GVWNGaRLZrrcdjLg50qTjJ6tlpgIgTNs X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI2MDEzMiBTYWx0ZWRfX9TI53MoVXlPl 6unlZT3WRnXgKRm4ITOg0wZ3lMa9F+4DJbMslOyJ6fAJW8qG5hU7Pjk4NF1Xinyg9L1fAT1tNst hMXBBcVVtGStcXtv9YpOAk3WqEdIu90= X-Proofpoint-GUID: GVWNGaRLZrrcdjLg50qTjJ6tlpgIgTNs X-Authority-Analysis: v=2.4 cv=MLpQXsZl c=1 sm=1 tr=0 ts=6a3ea28f cx=c_pps a=5HAIKLe1ejAbszaTRHs9Ug==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=WhMr71GatuKG99ydhcMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=gYDTvv6II1OnSo0itH1n:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-26_04,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 suspectscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606260132 On 6/22/26 12:11 AM, Doug Anderson wrote: > Hi, > > On Fri, Jun 19, 2026 at 8:34 AM Konrad Dybcio > wrote: [...] >>> >>> Are you sure that herobrine has 4 lanes routed on the PCB? >> >> +Doug any chance you still have schematics for that old boy? >> >> Bjorn, perhaps we could switch to a model where we define the max >> capabilities (i.e. 4-lane 8.1 GHz link) in the SoC DTs and only limit >> them as necessary? Not meeting these is borderline a board defect anyway > > Bleh, I'd forgotten what a pain it was to look at herobrine schematics > with the whole qcard "abstraction". > > My memory and a quick glance at schematics makes me say that herobrine > only has 2 lanes of DP. The problem is that this SoC really wasn't > designed with a laptop in mind. I seem to remember there only being > one USB 3 port and it is muxed with two of the DP lanes (since the SoC > is designed to drive a single Type-C port). In order to support all of > the ports that a laptop should have, you pretty much need to feed that > one USB 3 port into a USB hub and hardcode the DP to always use two > lanes. > > The two DP lanes then go to a mux where they can be routed either > towards the left Type C port or the right Type C port. > > In terms of whether we can support the 8.1 GHz link speed, I remember > much debate during the project, but I don't recall all the details. I > think the discussion was that we were supposed to support the higher > speeds, but we had to disable them because they weren't working. From > my fuzzy memory, it was unclear whether the problem was known to be > hardware or software related. I can try to dig deeper if it's > relevant. If anyone still has herobrine easily accessible, I guess a smoke test with a high res display and this: diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5c5e4f1dd221..a39e418fdabb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -464,7 +464,7 @@ &mdss_dp { &mdss_dp_out { data-lanes = <0 1>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; /* NVMe drive, enabled on a per-board basis */ would be the quickest way to confirm that. Although we can just leave it as-is if it's problematic.. I think you said there's some folks that still use it a couple years ago Konrad