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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b76f5162093sm429910166b.2.2025.11.28.03.04.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Nov 2025 03:04:15 -0800 (PST) Message-ID: Date: Fri, 28 Nov 2025 12:04:13 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] arm64: dts: qcom: sm8550: Enable UHS-I SDR50 and SDR104 SD card modes To: Vladimir Zapolskiy , Bjorn Andersson , Konrad Dybcio , Krzysztof Kozlowski Cc: Neil Armstrong , Rob Herring , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Sarthak Garg References: <20251126012043.3764567-1-vladimir.zapolskiy@linaro.org> <20251126012043.3764567-3-vladimir.zapolskiy@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: _VxtMu916XlEbqu8af6I8xbCSf1I4UzN X-Proofpoint-ORIG-GUID: _VxtMu916XlEbqu8af6I8xbCSf1I4UzN X-Authority-Analysis: v=2.4 cv=OPcqHCaB c=1 sm=1 tr=0 ts=692981b2 cx=c_pps a=DUEm7b3gzWu7BqY5nP7+9g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=BRLZTvTzQiK5oUZ-ObUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=-aSRE8QhW-JAV6biHavz:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI4MDA4MCBTYWx0ZWRfX4YEwApCuFeTj gyoMmD1gANlznDkMjEA/tVBNylPp3JFIqtIlWPt8vFgKToKUo8cRVyIelWb0eqINBKBqslp9HQe vmsRFNx8liPFBBDMPYtY7shO+2jtRAj/z9bH9uLG52vfGtFBcKfkAcCu/rvitq2M50tx0W2tEAs ajcF34RCrft8vwyQxLTnnUxocRu4nrEzNgHmp6SiUMtaKwJ7gzMZszHpbvZGl5WiuWn3AOiqYev cfEtu9vqCO0jpw7dabWoHt1fhCNnIOMFxXagpYgAvjo51UvZiwy5RcZKgts6qovf/x/Y4zzmIvV 0r8TEXL6t1nR1me420qtQ/bbeLTZwRDRJhSH5URAef3fRS9nXtjWk+5tGYmf9ZQnUPVXPe4xz6m Pa2lA+eOj57yeftGd40sVohyTPy3Eg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_03,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511280080 On 11/27/25 3:27 PM, Vladimir Zapolskiy wrote: > Hi Konrad. > > On 11/27/25 15:40, Konrad Dybcio wrote: >> On 11/26/25 2:20 AM, Vladimir Zapolskiy wrote: >>> The restriction on UHS-I speed modes was added to all SM8550 platforms >>> by copying it from SM8450 dtsi file, and due to the overclocking of SD >>> cards it was an actually reproducible problem. Since the latter issue >>> has been fixed, UHS-I speed modes are working fine on SM8550 boards, >>> below is the test performed on SM8550-HDK: >>> >>> SDR50 speed mode: >>> >>>      mmc0: new UHS-I speed SDR50 SDHC card at address 0001 >>>      mmcblk0: mmc0:0001 00000 14.6 GiB >>>       mmcblk0: p1 >>> >>>      % dd if=/dev/mmcblk0p1 of=/dev/null bs=1M count=1024 >>>      1024+0 records in >>>      1024+0 records out >>>      1073741824 bytes (1.1 GB, 1.0 GiB) copied, 23.5468 s, 45.6 MB/s >>> >>> SDR104 speed mode: >>> >>>      mmc0: new UHS-I speed SDR104 SDHC card at address 59b4 >>>      mmcblk0: mmc0:59b4 USDU1 28.3 GiB >>>       mmcblk0: p1 >>> >>>      % dd if=/dev/mmcblk0p1 of=/dev/null bs=1M count=1024 >>>      1024+0 records in >>>      1024+0 records out >>>      1073741824 bytes (1.1 GB, 1.0 GiB) copied, 11.9819 s, 89.6 MB/s >>> >>> Unset the UHS-I speed mode restrictions from the SM8550 platform dtsi >>> file, there is no indication that the SDHC controller is broken. >>> >>> Signed-off-by: Vladimir Zapolskiy >>> --- >> >> 8550 has additional limitations. One was addressed recently with >> max-sd-hs-hz (HS mode can only run at 37.5 MHz), but when in SDR104, >> the frequency must also be capped to 148 MHz. I don't know whether >> the driver respects that today. >> > > This frequency cap tuning for SDR104 speed mode is not done. If I > remember the story properly, the frequency cap for HS speed mode was > implemented in dts instead of being a pure Qualcomm SDHC specific > quirk, because it's possible to workaround the limitation by slightly > changing a board PCB layout. Then should this new SDR104 quirk be > considered due to a property in the dtb as well? I think so. > FWIW, comparing register dumps SD host controllers on SM8550 and SM8650 > SoCs are identical, should HS and SDR104 quirks be ported to SM8650 also? A document says that in 8650 and 8750 (and hamoa) and newer, these issues are not present, however the original author added the same limitation to sm8750: https://lore.kernel.org/linux-arm-msm/20251026111746.3195861-3-sarthak.garg@oss.qualcomm.com/ +Sarthak could you please remind us why it'd be necessary on !8550? Konrad