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Wed, 11 Dec 2024 12:50:13 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BBCoCuX026022 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 12:50:12 GMT Received: from [10.64.16.135] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 04:50:05 -0800 Message-ID: Date: Wed, 11 Dec 2024 20:50:02 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/8] phy: qcom: qmp-usbc: Add DP phy mode support on QCS615 To: Dmitry Baryshkov CC: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Kuogee Hsieh" , Vinod Koul , "Kishon Vijay Abraham I" , Linus Walleij , Bartosz Golaszewski , , , , , , , , , References: <20241129-add-displayport-support-for-qcs615-platform-v1-0-09a4338d93ef@quicinc.com> <20241129-add-displayport-support-for-qcs615-platform-v1-3-09a4338d93ef@quicinc.com> <5ea14162-567b-462d-be02-b73b954b7507@quicinc.com> <5whv4z7u6fkfwlv5muox5dmv6fow4mga76ammapw7wph7vwv3f@xibcjdfqorgf> <527baded-f348-48a8-81cd-3f84c0ff1077@quicinc.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: YEcBUSMTawlFVl6QGG7shl_PtInvRli7 X-Proofpoint-GUID: YEcBUSMTawlFVl6QGG7shl_PtInvRli7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110093 On 12/11/2024 5:46 PM, Dmitry Baryshkov wrote: > On Wed, Dec 11, 2024 at 08:46:16AM +0800, Xiangxu Yin wrote: >> >> >> On 12/10/2024 11:09 PM, Dmitry Baryshkov wrote: >>> On Thu, Dec 05, 2024 at 08:31:24PM +0200, Dmitry Baryshkov wrote: >>>> On Thu, Dec 05, 2024 at 09:26:47PM +0800, Xiangxu Yin wrote: >>>>> >>>>> >>>>> On 11/29/2024 10:33 PM, Dmitry Baryshkov wrote: >>>>>> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote: >>>>>>> >>>>>>> Extended DP support for QCS615 USB or DP phy. Differentiated between >>>>>>> USBC and DP PHY using the match table’s type, dynamically generating >>>>>>> different types of cfg and layout attributes during initialization based >>>>>>> on this type. Static variables are stored in cfg, while parsed values >>>>>>> are organized into the layout structure. >>>>>> >>>>>> We didn't have an understanding / conclusion whether >>>>>> qcom,usb-ssphy-qmp-usb3-or-dp PHYs are actually a single device / PHY >>>>>> or two PHYs being placed next to each other. Could you please start >>>>>> your commit message by explaining it? Or even better, make that a part >>>>>> of the cover letter for a new series touching just the USBC PHY >>>>>> driver. DP changes don't have anything in common with the PHY changes, >>>>>> so you can split the series into two. >>>>>> >>>>> Before implement DP extension, we have discussed with abhinav and krishna about whether use combo, usbc or separate phy. >>>> >>>> What is "DP extension"? >>>> >> I'm sorry confusion casued by my description. It's means extend DP implemnt for USBC phy driver. >>>>> >>>>> We identified that DP and USB share some common controls for phy_mode and orientation. >>>>> Specifically, 'TCSR_USB3_0_DP_PHYMODE' controls who must use the lanes - USB or DP, >>>>> while PERIPH_SS_USB0_USB3PHY_PCS_MISC_TYPEC_CTRL controls the orientation. >>>>> It would be more efficient for a single driver to manage these controls. >>>> >>>> The question is about the hardware, not about the driver. >>>> >>>>> Additionally, this PHY does not support Alt Mode, and the two control registers are located in separate address spaces. >>>>> Therefore, even though the orientation for DP on this platform is always normal and connected to the video output board, >>>>> we still decided to base it on the USBC extension. >>>> >>>> Could you please clarify, do usb3-or-dp PHYs support DP-over-USB-C? I >>>> thought that usbc-or-dp platforms support that, but they don't >>>> support DP+USB pin configuration. Note, the question is broader than >>>> just QCS615, it covers the PHY type itself. >>>> >>>> Also, is TCSR configuration read/write or read-only? Are we supposed to >>>> set the register from OS or are we supposed to read it and thus detemine >>>> the PHY mode? >>> >>> Any updates on these two topics? >>> >> Still confirming detail info with HW & design team. >> I’ll update the information that has been confirmed so far. >> This phy support DP-over-USB-C,but it's not support alt-mode which 2 lane work for DP, other 2 lane work for USB. >> TCSR phy mode is read/write reg and we can read for determine phy mode. > > Ok, thanks for the explanation. From my point of view: > > - Implement the DP PHY to be a part of the same driver. Each device > supported by the usbc driver should get both PHYs. > > - Make sure not to break the ABI: #phy-cells = <0> should still work and > return USB PHY, keeping backwards compatibility. Newer devices or > upgraded DT for old devices should return USB PHY for <... 0> and DP > PHY for <... 1>. > Yes, currently we have implemented like your description, Each deivce shoud get both PHYs, DP PHY for <... 1> and USB PHY for <... 0>. > - I'm not shure how to handle the USB and DP coexistence, especially in > your case of the USB-or-DP PHY. > For coexistence process: When we start implement DP part, usb driver team said only need config TCSR phy mode and orientation during switch in USB-C port. Based on your previous comments avout SW_PWRDN, I'm confirming with the USB team whether SW_REST/SWPWRDN/START_CTRL registers might affect DP. Anyway, even though the original SoC design supports DP or USB over Type-C， but on QCS615 ADP AIR platform, there are only four USB-A port which works with 'qcs615-qmp-usb3-phy' driver, and no USB-C port. DP port is mappped from usb pin to the video out sub-board. so we are unable to verify the switching case between DP and USB devices under USB-C. However, I'm also confirming whether anything other will affect USB and DP each other.