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Tue, 31 Oct 2023 06:44:16 GMT Received: from [10.214.225.95] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 23:44:10 -0700 Message-ID: Date: Tue, 31 Oct 2023 12:14:07 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 7/9] arm64: dts: qcom: sc7280: Add CDSP node Content-Language: en-US To: Doug Anderson , Luca Weiss CC: Andy Gross , Bjorn Andersson , Konrad Dybcio , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , , <~postmarketos/upstreaming@lists.sr.ht>, , Krzysztof Kozlowski , Rob Herring , =?UTF-8?Q?Matti_Lehtim=c3=a4ki?= , , , , References: <20231027-sc7280-remoteprocs-v1-0-05ce95d9315a@fairphone.com> <20231027-sc7280-remoteprocs-v1-7-05ce95d9315a@fairphone.com> <7934a36a-9438-719a-2ed0-4a78757b044b@quicinc.com> From: Mukesh Ojha In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Rhgh_dG_VXDdBDu2mFsR1Lk5K0QmyRH3 X-Proofpoint-ORIG-GUID: Rhgh_dG_VXDdBDu2mFsR1Lk5K0QmyRH3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 phishscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310051 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 10/30/2023 8:33 PM, Doug Anderson wrote: > Hi, > > On Mon, Oct 30, 2023 at 7:43 AM Luca Weiss wrote: >> >> On Mon Oct 30, 2023 at 3:11 PM CET, Doug Anderson wrote: >>> Hi, >>> >>> On Mon, Oct 30, 2023 at 2:12 AM Luca Weiss wrote: >>>> >>>> On Mon Oct 30, 2023 at 10:04 AM CET, Mukesh Ojha wrote: >>>>> >>>>> >>>>> On 10/27/2023 7:50 PM, Luca Weiss wrote: >>>>>> Add the node for the ADSP found on the SC7280 SoC, using standard >>>>>> Qualcomm firmware. >>>>>> >>>>>> The memory region for sc7280-chrome-common.dtsi is taken from msm-5.4 >>>>>> yupik.dtsi since the other areas also seem to match that file there, >>>>>> though I cannot be sure there. >>>>>> >>>>>> Signed-off-by: Luca Weiss >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 + >>>>>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++ >>>>>> 2 files changed, 143 insertions(+) >>>>>> >>>>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi >>>>>> index eb55616e0892..6e5a9d4c1fda 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi >>>>>> @@ -29,6 +29,11 @@ adsp_mem: memory@86700000 { >>>>>> no-map; >>>>>> }; >>>>>> >>>>>> + cdsp_mem: memory@88f00000 { >>>>>> + reg = <0x0 0x88f00000 0x0 0x1e00000>; >>>>>> + no-map; >>>>>> + }; >>>>>> + >>>>> >>>>> Just a question, why to do it here, if chrome does not use this ? >>>> >>>> Other memory regions in sc7280.dtsi also get referenced but not actually >>>> defined in that file, like mpss_mem and wpss_mem. Alternatively we can >>>> also try and solve this differently, but then we should probably also >>>> adjust mpss and wpss to be consistent. >>>> >>>> Apart from either declaring cdsp_mem in sc7280.dtsi or >>>> "/delete-property/ memory-region;" for CDSP I don't really have better >>>> ideas though. >>>> >>>> I also imagine these ChromeOS devices will want to enable cdsp at some >>>> point but I don't know any plans there. >>> >>> Given that "remoteproc_cdsp" has status "disabled" in the dtsi, it >>> feels like the dtsi shouldn't be reserving memory. I guess maybe >>> memory regions can't be status "disabled"? >> >> Hi Doug, >> >> That's how it works in really any qcom dtsi though. I think in most/all >> cases normally the reserved-memory is already declared in the SoC dtsi >> file and also used with the memory-region property. >> >> I wouldn't be against adjusting sc7280.dtsi to match the way it's done >> in the other dtsi files though, so to have all the required labels >> already defined in the dtsi so it doesn't rely on these labels being >> defined in the device dts. >> >> In other words, currently if you include sc7280.dtsi and try to build, >> you first have to define the labels mpss_mem and wpss_mem (after this >> patch series also cdsp_mem and adsp_mem) for it to build. >> >> I'm quite neutral either way, let me know :) > > I haven't done a ton of thinking about this, so if I'm spouting > gibberish then feel free to ignore me. :-P It just feels weird that > when all the "dtsi" files are combined and you look at what you end up > on a sc7280 Chrome board that you'll be reserving 32MB of memory for a > device that's set (in the same device tree) to be "disabled", right? > ...the 32MB is completely wasted, I think. If we wanted to enable the > CDSP we'd have to modify the device tree anyway, so it seems like that > same modification would set the CDSP to "okay" and also reserve the > memory... > > In that vein, it seems like maybe you could move the "cdsp_mem" to the > SoC .dsti file with a status of "disabled". . I guess we don't do that > elsewhere, but maybe we should be? As far as I can tell without > testing it (just looking at fdt_scan_reserved_mem()) this should > work... What do you think about moving present reserve memory block from sc7280-chrome-common to sc7280.dtsi and delete the stuff which chrome does not need it sc7280-chrome-common ? -Mukesh > > -Doug