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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: RQ_DJpEWNOr5OmDokndiAH_xh3_5AUfe X-Proofpoint-GUID: RQ_DJpEWNOr5OmDokndiAH_xh3_5AUfe X-Authority-Analysis: v=2.4 cv=NdLm13D4 c=1 sm=1 tr=0 ts=68c15990 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=3WXPGMdjBYCeSjfzpvMA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA4MDA2NiBTYWx0ZWRfXynjQXmfkgUZq C+p6Z3+lAw4BF6vo85PP6/UpUTyxnU36aAl6kGc5UvezBnlHRIzuJrUzHDn3Wqbgsf0OEZpWM7T Bcw+SJE+TGTWsVAzKTvuqK3XYvQeg6M3a9iGjtdcyUw/JwDBVxTUcdOVPBvTrl2ct8C4Og4Xg85 /7sk9sCaQl5PAt8BMzhcgsPfsgidUtC91LpCp71jza7VLCK3Z2MkiqKVBcL5UNUTy+LXkh+wexD JnkEY29a5DFSeR0LXuiTQ4BBeOueulINkQyrj0gpc3uqJLl7ChqpqsQ1XLQM0LqssRWD3XZqNim iAAbBlBuSognDl8fQ+/GyqbaloRy4zL2oygQ8QbnBCdwv+vjHJ38GVwH5yeQwDbePU0e6m5XKpf MbWGMEug X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-09_03,2025-09-10_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509080066 On 9/4/2025 8:01 PM, Konrad Dybcio wrote: > The hardware requires the faster of the two (37.5 MHz as opposed to > 19.2 MHz) clock rates to hit the required timings for I2C Fast+ Mode. Should mention "source clock rates" to not confuse with derived frequency/timings for Fast+ mode.> > Additionally, the magic presets for electrical tuning registers on SoCs > supporting that faster mode ("cci_v2" in the driver) are calculated are/is calculated> based on that faster frequency. > > Moreover, while its unlikely that it would ever exhibit as an issue > given CCI is a slow & tiny core, we do need to express a minimal voltage > level for any given clock rate, which is where the (optional - > backwards compat) OPP table addition comes in. > > This series helps ensure all these requirements are met. > > Patch 1 is a related but independent fix, can be picked right away > Patch 5 can be functionally merged as-is, but depends on patch 2 for > bindings > > Signed-off-by: Konrad Dybcio > --- > Konrad Dybcio (5): > arm64: dts: qcom: sc8280xp: Fix CCI3 interrupt > dt-bindings: i2c: qcom-cci: Allow operating-points-v2 > i2c: qcom-cci: Drop single-line wrappers > i2c: qcom-cci: Add OPP table support and enforce FAST_PLUS requirements > arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts > > .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 + > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 +++++++- > drivers/i2c/busses/i2c-qcom-cci.c | 45 +++++++++++++++++----- > 3 files changed, 52 insertions(+), 11 deletions(-) > --- > base-commit: 4ac65880ebca1b68495bd8704263b26c050ac010 > change-id: 20250904-topic-cci_updates-800fdc9bada4 > > Best regards,