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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d149a25924sm2113819a12.17.2024.12.06.04.20.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Dec 2024 04:20:22 -0800 (PST) Message-ID: Date: Fri, 6 Dec 2024 13:20:18 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 44/45] arm64: dts: qcom: add mst support for pixel stream clk for DP0 To: Abhinav Kumar , Rob Clark , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Stephen Boyd , Chandan Uddaraju , Guenter Roeck , Kuogee Hsieh , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Vara Reddy , Rob Clark , Tanmay Shah , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jessica Zhang , Laurent Pinchart , Yongxing Mou References: <20241205-dp_mst-v1-0-f8618d42a99a@quicinc.com> <20241205-dp_mst-v1-44-f8618d42a99a@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241205-dp_mst-v1-44-f8618d42a99a@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: uXVIxB6iGksbZYDU_0_J1fFhB_FhGSmZ X-Proofpoint-ORIG-GUID: uXVIxB6iGksbZYDU_0_J1fFhB_FhGSmZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 malwarescore=0 bulkscore=0 mlxlogscore=874 mlxscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412060091 On 6.12.2024 5:32 AM, Abhinav Kumar wrote: > From: Yongxing Mou > > Populate the pixel clock for stream 1 for DP0 for sa8775p DP controller. > > Signed-off-by: Yongxing Mou > Signed-off-by: Abhinav Kumar > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 0dbaa17e5e3f06c61b2aa777e45b73a48e50e66b..0150ce27b98e9894fa9ee6cccd020528d716f543 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -3944,16 +3944,20 @@ mdss0_dp0: displayport-controller@af54000 { > <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, > <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; dispcc also defines PIXEL2/3 clocks. > clock-names = "core_iface", > "core_aux", > "ctrl_link", > "ctrl_link_iface", > - "stream_pixel"; > + "stream_pixel", > + "stream_1_pixel"; > assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, > + <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; > + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, <&mdss0_dp0_phy 1>; Please turn this into a vertical list Konrad