* [PATCH v2] arm64: dts: qcom: qcs8300: add the pcie smmu node
@ 2025-04-29 10:09 Pratyush Brahma
2025-04-30 10:18 ` Konrad Dybcio
0 siblings, 1 reply; 2+ messages in thread
From: Pratyush Brahma @ 2025-04-29 10:09 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Pratyush Brahma
Add the PCIe SMMU node to enable address translations
for pcie.
Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
---
Changes in v2:
- Updated the global-interrupts and interrupts based on Konrad's suggestions
- Link to v1: https://lore.kernel.org/r/20250206-qcs8300-pcie-smmu-v1-1-8eee0e3585bc@quicinc.com
---
arch/arm64/boot/dts/qcom/qcs8300.dtsi | 74 +++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..5d15e2d77003d1f2e14e1d43a29330a67a070a07 100644
--- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
@@ -3199,6 +3199,80 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>;
};
+ pcie_smmu: iommu@15200000 {
+ compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15200000 0x0 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ dma-coherent;
+
+ interrupts = <GIC_SPI 922 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>,
---
base-commit: a13f6e0f405ed0d3bcfd37c692c7d7fa3c052154
change-id: 20250206-qcs8300-pcie-smmu-4c8121c739e8
Best regards,
--
Pratyush Brahma <quic_pbrahma@quicinc.com>
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v2] arm64: dts: qcom: qcs8300: add the pcie smmu node
2025-04-29 10:09 [PATCH v2] arm64: dts: qcom: qcs8300: add the pcie smmu node Pratyush Brahma
@ 2025-04-30 10:18 ` Konrad Dybcio
0 siblings, 0 replies; 2+ messages in thread
From: Konrad Dybcio @ 2025-04-30 10:18 UTC (permalink / raw)
To: Pratyush Brahma, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 4/29/25 12:09 PM, Pratyush Brahma wrote:
> Add the PCIe SMMU node to enable address translations
> for pcie.
>
> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
> ---
> Changes in v2:
> - Updated the global-interrupts and interrupts based on Konrad's suggestions
There was another discussion on a similar ambiguous numbering issue
on the related sa8775p, and now I'm beyond confused. Please ask
someone internally to confirm these numbers.
Konrad
^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-04-30 10:18 ` Konrad Dybcio
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