From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34EACC4363D for ; Wed, 23 Sep 2020 15:24:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C62923119 for ; Wed, 23 Sep 2020 15:24:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726674AbgIWPY6 (ORCPT ); Wed, 23 Sep 2020 11:24:58 -0400 Received: from foss.arm.com ([217.140.110.172]:48892 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726670AbgIWPY6 (ORCPT ); Wed, 23 Sep 2020 11:24:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75450113E; Wed, 23 Sep 2020 08:24:57 -0700 (PDT) Received: from [10.57.48.76] (unknown [10.57.48.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 739473F718; Wed, 23 Sep 2020 08:24:55 -0700 (PDT) Subject: Re: [PATCHv5 5/6] iommu: arm-smmu-impl: Use table to list QCOM implementations To: Sai Prakash Ranjan , Will Deacon , Joerg Roedel , Jordan Crouse , Rob Clark Cc: iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Akhil P Oommen , Bjorn Andersson , freedreno@lists.freedesktop.org, "Kristian H . Kristensen" , dri-devel@lists.freedesktop.org References: From: Robin Murphy Message-ID: Date: Wed, 23 Sep 2020 16:24:53 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.2.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2020-09-22 07:18, Sai Prakash Ranjan wrote: > Use table and of_match_node() to match qcom implementation > instead of multiple of_device_compatible() calls for each > QCOM SMMU implementation. > > Signed-off-by: Sai Prakash Ranjan > --- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > index d199b4bff15d..ce78295cfa78 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > @@ -9,6 +9,13 @@ > > #include "arm-smmu.h" > > +static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { > + { .compatible = "qcom,sc7180-smmu-500" }, > + { .compatible = "qcom,sdm845-smmu-500" }, > + { .compatible = "qcom,sm8150-smmu-500" }, > + { .compatible = "qcom,sm8250-smmu-500" }, > + { } > +}; Can you push the table itself into arm-smmu-qcom? That way you'll be free to add new SoCs willy-nilly without any possibility of conflicting with anything else. Bonus points if you can fold in the Adreno variant and keep everything together ;) Robin. > static int arm_smmu_gr0_ns(int offset) > { > @@ -217,10 +224,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > if (of_device_is_compatible(np, "nvidia,tegra194-smmu")) > return nvidia_smmu_impl_init(smmu); > > - if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") || > - of_device_is_compatible(np, "qcom,sc7180-smmu-500") || > - of_device_is_compatible(np, "qcom,sm8150-smmu-500") || > - of_device_is_compatible(np, "qcom,sm8250-smmu-500")) > + if (of_match_node(qcom_smmu_impl_of_match, np)) > return qcom_smmu_impl_init(smmu); > > if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) >