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[192.35.156.11]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29246fcbe80sm7840285ad.29.2025.10.17.17.20.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Oct 2025 17:20:28 -0700 (PDT) Message-ID: Date: Fri, 17 Oct 2025 17:20:26 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v5 02/10] dt-bindings: phy: qcom,qmp-usb: Add Glymur USB UNI PHY compatible Content-Language: en-US To: Krzysztof Kozlowski , krzk+dt@kernel.org, conor+dt@kernel.org, konrad.dybcio@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, kishon@kernel.org, vkoul@kernel.org, gregkh@linuxfoundation.org, robh@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251006222002.2182777-1-wesley.cheng@oss.qualcomm.com> <20251006222002.2182777-3-wesley.cheng@oss.qualcomm.com> <00408896-2e25-2dd1-6e6e-2195317ee7fb@oss.qualcomm.com> <14bc2a85-0f1d-3834-9b9c-32654348603a@oss.qualcomm.com> <387c707e-613d-433b-a76d-16ef10dabc59@kernel.org> <2a70f878-269c-1b40-2e8c-77b5851de9a1@oss.qualcomm.com> <99ab26d3-eb44-401d-8a7c-1d9efd2a1a10@kernel.org> From: Wesley Cheng In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: OnqtnwhAIFnjfWgjX8DbID5ZNmCccFPe X-Proofpoint-ORIG-GUID: OnqtnwhAIFnjfWgjX8DbID5ZNmCccFPe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAyMCBTYWx0ZWRfX6FlPPEjLcNS8 NcjYov2lduzzymnjqaLGyVHPLpFTIhtXvCb7R8MXzCqBbo2Vi00yEEVP/kcWUuwdr6NhAUPEIsA Z8jCihR6V+YOLKNuv0/Gyod1l2GhCzcGV/zLriMud/jtaQA4ohffAqezFqywt88n0iA4NDGQmWw 0qQ03e5itxwLkxtpOhEPb5Jo3tj7EmrWhQ2+eYY+tkcbbRhvrOyX8CxGuHwBv+S3fZl+xIK8afs hK5YS5USz8uR1HfaDWtrHi5sw5AqDQLGsqIkauIOs/4AFq9SNvrIcsJiGt4kCkSPUoYmUK3WC5G N5w751zAEebevy8dOIozlvIwyHOJhL5tWnqvQe8hun+/X6XhbNdAqGOELRGzwWLXMktGr6Zlam4 QfYXku9FY2A/i1cQzl9HE4O3lADYXg== X-Authority-Analysis: v=2.4 cv=V71wEOni c=1 sm=1 tr=0 ts=68f2dd4f cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZdW6uxA9NKXbfdqeeS2OGA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=JAPtGALJ81qCqeSEnE8A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-17_08,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110020 On 10/16/2025 9:41 PM, Krzysztof Kozlowski wrote: > On 17/10/2025 02:15, Wesley Cheng wrote: >>>> Technically its all handling the same clock branch (CXO), we have the >>>> TCSR clkref register that allows us to gate the CXO to the USB PHY, as >>> >>> >>> Ah, exactly. Then clkref is not a clock. You need rather proper clock >>> hierarchy. >>> >>>> CXO is shared across several HW blocks, so it allows us to properly >>>> powerdown the PHY even though other clients are voting for CXO on. Then >>>> we obviously have to remove our vote to the overall CXO, so that it can >>>> potentially be shutdown. >>>> >>>> Maybe we can rename it to "clkref" for the CXO handle and >>>> "clkref_switch" for the TCSRCC handle? >>> >>> Naming is better, but it is still not correct. This is not independent >>> clock signal. It is the same clock. >>> >> >> Hmmm... I guess that's why I kept the same clkref tag, to denote that >> its the same clock, but one is a switch/gate for it. Would you happen >> to have any suggestions you might have that makes it clearer for >> everyone to understand? > To me it looks like: > > |-----| |-----------| |------------------| > |clock|------------|TCSRCC gate|-----------|clkref to this dev| > |-----| |-----------| |------------------| > > So you need proper clock controller for TCSR (TCSR Clock Controller, in > short TCSRCC, what a surprise!) which will take input, add gate and > produce clock for this device. > > Nothing non-standard, all Qualcomm SoCs have it, every other platform > has it in some way. > Hi Krzystof, Yes, the design is exactly how you outlined it above. How about clkref for the clock and tcsrcc_switch for the clkref switch? That removes any notation that the gate/switch is an actual clock... Thanks Wesley Cheng