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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b8c0d2364d5sm3941558a12.19.2025.10.30.00.21.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Oct 2025 00:21:19 -0700 (PDT) Message-ID: Date: Thu, 30 Oct 2025 15:21:09 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 3/4] arm64: dts: qcom: Add DisplayPort and QMP USB3DP PHY for SM6150 To: Bjorn Andersson Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com, Dmitry Baryshkov , Konrad Dybcio References: <20251024-add-displayport-support-to-qcs615-devicetree-v6-0-c4316975dd0e@oss.qualcomm.com> <20251024-add-displayport-support-to-qcs615-devicetree-v6-3-c4316975dd0e@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDA1OCBTYWx0ZWRfX/Cme+RLp+8J+ WYGyQeaCv9Qk8FXCgWabbVGb43FzUDCxnVc5oUmyeVkGTyie6oVgzpSyahfhSlM1y6Cgsu0U1GI Mi2U2L05ITdu1k2Wi+lAkSkdG1d3vCAmVml6SJ0mXCli6Tckei6i0MgRFr7eU0rG0lzmrF1AIvg 1rD/2gTOADpyatlEWGYYJICHlpU9WC7oehmqMFztBoY/Y7Ya4mPGa8gM/LhBFlxC/yPJg+K2vxR q97PP9yEN89rPRCl05uZ5srUL+LVsN/wU+uRgRLoC3EGsTP7/72oGZEkAAt/crEk8khoL+nK2ca FO7G5RKlXd4Ir7gKTCCvuEkSCCQn0uofTlPvjaimmkfGTwr/6IYbOgkAwOcoynNbpfnDm0CsREz fzS2QMan1jLnlGrY2dWQ6orzj5bTmw== X-Proofpoint-ORIG-GUID: bh9-oEJnsGWG_1JbI8Q3TywIau03Ymdr X-Authority-Analysis: v=2.4 cv=V+RwEOni c=1 sm=1 tr=0 ts=690311f1 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=tU0UsG_G8rlFAKuj474A:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: bh9-oEJnsGWG_1JbI8Q3TywIau03Ymdr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_01,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300058 On 10/30/2025 1:32 AM, Bjorn Andersson wrote: > On Fri, Oct 24, 2025 at 01:21:03PM +0800, Xiangxu Yin via B4 Relay wrote: >> From: Xiangxu Yin >> > Please fix the subject prefix and drop the "for SM6150" suffix. > > Regards, > Bjorn Ok, due to sm6150.dtsi have renamed to talos.dtsi in newest version. Will update to 'arm64: dts: qcom: talos: Add DisplayPort and QMP USB3DP PHY' >> Introduce DisplayPort controller node and associated QMP USB3-DP PHY >> for SM6150 SoC. Add data-lanes property to the DP endpoint and update >> clock assignments for proper DP integration. >> >> Reviewed-by: Dmitry Baryshkov >> Reviewed-by: Konrad Dybcio >> Signed-off-by: Xiangxu Yin >> --- >> arch/arm64/boot/dts/qcom/sm6150.dtsi | 115 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 113 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi >> index 6128d8c48f9c0807ac488ddac3b2377678e8f8c3..9741f8d14c72ed7dd6a5e483c5c0d578662f1d31 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi >> @@ -14,6 +14,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -3717,6 +3718,7 @@ port@0 { >> reg = <0>; >> >> dpu_intf0_out: endpoint { >> + remote-endpoint = <&mdss_dp0_in>; >> }; >> }; >> >> @@ -3749,6 +3751,89 @@ opp-307200000 { >> }; >> }; >> >> + mdss_dp0: displayport-controller@ae90000 { >> + compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; >> + >> + reg = <0x0 0x0ae90000 0x0 0x200>, >> + <0x0 0x0ae90200 0x0 0x200>, >> + <0x0 0x0ae90400 0x0 0x600>, >> + <0x0 0x0ae90a00 0x0 0x600>, >> + <0x0 0x0ae91000 0x0 0x600>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <12>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel", >> + "stream_1_pixel"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; >> + assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, >> + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, >> + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; >> + >> + phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; >> + phy-names = "dp"; >> + >> + operating-points-v2 = <&dp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + >> + #sound-dai-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + mdss_dp0_in: endpoint { >> + remote-endpoint = <&dpu_intf0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + mdss_dp0_out: endpoint { >> + data-lanes = <3 2 0 1>; >> + }; >> + }; >> + }; >> + >> + dp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-160000000 { >> + opp-hz = /bits/ 64 <160000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-270000000 { >> + opp-hz = /bits/ 64 <270000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-540000000 { >> + opp-hz = /bits/ 64 <540000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + }; >> + }; >> + >> mdss_dsi0: dsi@ae94000 { >> compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; >> reg = <0x0 0x0ae94000 0x0 0x400>; >> @@ -3844,8 +3929,8 @@ dispcc: clock-controller@af00000 { >> <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, >> <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, >> <0>, >> - <0>, >> - <0>; >> + <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, >> + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; >> >> #clock-cells = <1>; >> #reset-cells = <1>; >> @@ -4214,6 +4299,32 @@ usb_qmpphy: phy@88e6000 { >> status = "disabled"; >> }; >> >> + usb_qmpphy_2: phy@88e8000 { >> + compatible = "qcom,qcs615-qmp-usb3-dp-phy"; >> + reg = <0x0 0x088e8000 0x0 0x2000>; >> + >> + clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, >> + <&gcc GCC_USB3_SEC_CLKREF_CLK>, >> + <&gcc GCC_AHB2PHY_WEST_CLK>, >> + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; >> + clock-names = "aux", >> + "ref", >> + "cfg_ahb", >> + "pipe"; >> + >> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, >> + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; >> + reset-names = "phy_phy", >> + "dp_phy"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <1>; >> + >> + qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; >> + >> + status = "disabled"; >> + }; >> + >> usb_1: usb@a6f8800 { >> compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; >> reg = <0x0 0x0a6f8800 0x0 0x400>; >> >> -- >> 2.34.1 >> >>