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Fri, 15 May 2026 01:29:45 -0700 (PDT) X-Received: by 2002:a05:622a:a6d2:b0:50d:9f3e:e1a with SMTP id d75a77b69052e-5164155af1emr72148901cf.9.1778833784838; Fri, 15 May 2026 01:29:44 -0700 (PDT) Received: from [192.168.68.112] ([5.133.47.210]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-48fe53ab671sm43751045e9.1.2026.05.15.01.29.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 May 2026 01:29:44 -0700 (PDT) Message-ID: Date: Fri, 15 May 2026 08:29:43 +0000 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] arm64: dts: qcom: agatti: add LPASS devices To: Konrad Dybcio , lee@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, sboyd@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alexey.klimov@linaro.org, r.mereu@arduino.cc, srini@kenrel.org References: <20260223133950.221234-1-srinivas.kandagatla@oss.qualcomm.com> <20260223133950.221234-4-srinivas.kandagatla@oss.qualcomm.com> <07cb095b-7765-4810-a8e3-db2bd9ba6276@oss.qualcomm.com> Content-Language: en-US From: Srinivas Kandagatla In-Reply-To: <07cb095b-7765-4810-a8e3-db2bd9ba6276@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE1MDA4NCBTYWx0ZWRfX6aOrkBwO7d0x TS9B//CFnhJ8sGpuYnpQGGsuY7DS/MqaW4dKkfoGLsZrt3UG8wQ2nSv5eb2H/8iUKDzQ3OjMOZb 1cgn+alFK2uYVqVnvsx94ShOXgS3/Mjo3pSVVK4eTg0A2YwgZiJ76wPAcUJpjmNRsT7jpHERvXN a1GbPJLtGLsyX8slMzWfXAJi4S3G2sHIPXx0Wx1SaNVgIdD4cX647jhcy2nUWmN8YA83nnp6+o7 lukkjbvX0qrueO0AP3b/rJG5Aw7Dc7LARoMWqYRu9wNgYuI58Ypd5tdjzOKiu1eXysqoI2t+Q+O IA+cwE2ZytrDM69yRHhm9h38pyyP5XKs7JZgXX+te7sUrYk8nKVw0FSgbcZmn2vVjQUosD4/u9y tsfCAvqW9/QcBzdijT84IU4PgDZj4zA1Uhg4ShBvU9CS8PuYLr4bOLbOR+eV2a/ck98EKpz0xLO 0vcqiuAbP7FgUjgFzpA== X-Authority-Analysis: v=2.4 cv=cZXiaHDM c=1 sm=1 tr=0 ts=6a06d979 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=ZsC4DHZuhs/kKio7QBcDoQ==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=APSRQGo-bA5DRRouejwA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: YXS-a7JacLX9cfah518_4ppeklCD64uF X-Proofpoint-ORIG-GUID: YXS-a7JacLX9cfah518_4ppeklCD64uF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-15_02,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605150084 On 2/24/26 12:28 PM, Konrad Dybcio wrote: > On 2/23/26 2:39 PM, Srinivas Kandagatla wrote: >> From: Alexey Klimov >> >> The rxmacro, txmacro, vamacro, soundwire nodes, lpass clock >> controllers are required to support audio playback and >> audio capture on sm6115 and its derivatives. >> >> Signed-off-by: Alexey Klimov >> Signed-off-by: Srinivas Kandagatla >> --- > > [...] > >> + lpass_audiocc: clock-controller@a6a9000 { >> + compatible = "qcom,sm6115-lpassaudiocc"; >> + reg = <0x0 0x0a6a9000 0x0 0x1000>; >> + #reset-cells = <1>; >> + }; > > This should be called "qcom,sm6115-lpass-audio-csr" and should probably > have a syscon fallback as there's a lot of various magic tunables in > there, in addition to the CGCR bits. The clock driver can continue to > bind to this new compatible, like we do with the SoC-side TCSR on e.g. > 8550 and the tcsrcc-sm8550 driver. Are you expecting this to be a reset-controller interface or just syscon so that drivers can poke into this register space. The reason to take the full address space here and represent the HW control bits as reset controller is that we have room for adding these various magic tunables with some standard interface when required in this driver. I could have done the way as you suggested with syscon and let the drivers poke the whatever values it want, but that is not scalable and clutters the interfaces and encourage to use the way it was done in downstream. This is same for all the Qualcomm SoCs, why sm6115 has to do this change alone? And its going to break the Device tree abi. Sorry but I can not do the changes that you suggested here. I would suggest that we use the existing mechanism which is more future proof. Please suggest otherwise, I would like to move on with enabling audio on UNO Q platform. --srini > > [...] > >> + lpasscc: clock-controller@a7ec000 { >> + compatible = "qcom,sm6115-lpasscc"; >> + reg = <0x0 0x0a7e0000 0x0 0x12000>; >> + #reset-cells = <1>; >> + }; > > All the same, except "qcom,sm6115-lpass-tcsr" > > I'm once again sorry for not getting this right n years ago, but I did not > have the sufficient documentation back then > > Konrad