From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 965FAC433F5 for ; Thu, 3 Mar 2022 23:40:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235900AbiCCXlN (ORCPT ); Thu, 3 Mar 2022 18:41:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231128AbiCCXlN (ORCPT ); Thu, 3 Mar 2022 18:41:13 -0500 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9C331375B3 for ; Thu, 3 Mar 2022 15:40:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646350826; x=1677886826; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=WWMIm6HjjY0kxnD7nyPXZtP5nGZ/E5M1aZ4oLPWnKe0=; b=Z5RvoRntTAfwK7hmGxc1lgg51u9HvfkcePEaUVl22OmDMCn4xBbQsaMH VNvLmAQ5YV/zW3PUcIIBmj5LTLo32E7zlSniY8wk6h2j4nnzQVs5/b0PL 6VMlv7tBojTqqvWFlcGTfaxlIupzkoNNJhbSo9ENOon48h+GXEsHoBcfe Y=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 03 Mar 2022 15:40:26 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2022 15:40:26 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 3 Mar 2022 15:40:25 -0800 Received: from [10.110.60.142] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 3 Mar 2022 15:40:24 -0800 Message-ID: Date: Thu, 3 Mar 2022 15:40:24 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH 00/12] Add writeback block support for DPU Content-Language: en-US To: Stephen Boyd , CC: , , , , , , , , , References: <1644009445-17320-1-git-send-email-quic_abhinavk@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Stephen There is some discussion going on about the base dependency of the change: https://patchwork.kernel.org/project/dri-devel/patch/20220202085429.22261-6-suraj.kandpal@intel.com/ I will resend this with comments addressed once the dependency is sorted out among intel, QC and laurent. Thanks Abhinav On 3/3/2022 2:46 PM, Stephen Boyd wrote: > Quoting Abhinav Kumar (2022-02-04 13:17:13) >> This series adds support for writeback block on DPU. Writeback >> block is extremely useful to validate boards having no physical displays >> in addition to many other use-cases where we want to get the output >> of the display pipeline to examine whether issue is with the display >> pipeline or with the panel. > > Is this series going to be resent?