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[2001:14bb:c2:310f:a0b3:1d12:b116:f8e6]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-30d7d910e70sm2720771fa.105.2025.03.21.09.23.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Mar 2025 09:23:46 -0700 (PDT) Message-ID: Date: Fri, 21 Mar 2025 18:23:45 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm6350: Add video clock controller To: Luca Weiss Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250321-sm6350-videocc-v1-0-c5ce1f1483ee@fairphone.com> <20250321-sm6350-videocc-v1-3-c5ce1f1483ee@fairphone.com> Content-Language: en-US From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: UC6SnHFTts8evORxaGOmy6OnD6QJLRsR X-Authority-Analysis: v=2.4 cv=ZtHtK87G c=1 sm=1 tr=0 ts=67dd9295 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=6H0WHjuAAAAA:8 a=5zAZ7Tx_SugcLKjGGPAA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-GUID: UC6SnHFTts8evORxaGOmy6OnD6QJLRsR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-21_05,2025-03-21_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 phishscore=0 priorityscore=1501 impostorscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503210120 On 21/03/2025 18:15, Luca Weiss wrote: > Hi Dmitry, > > On Fri Mar 21, 2025 at 4:56 PM CET, Dmitry Baryshkov wrote: >> On Fri, Mar 21, 2025 at 03:45:01PM +0100, Luca Weiss wrote: >>> Add a node for the videocc found on the SM6350 SoC. >>> >>> Signed-off-by: Luca Weiss >>> --- >>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 14 ++++++++++++++ >>> 1 file changed, 14 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> index 00ad1d09a19558d9e2bc61f1a81a36d466adc88e..ab7118b4f8f8cea56a3957e9df67ee1cd74820a6 100644 >>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>> @@ -1952,6 +1952,20 @@ usb_1_dwc3_ss_out: endpoint { >>> }; >>> }; >>> >>> + videocc: clock-controller@aaf0000 { >>> + compatible = "qcom,sm6350-videocc"; >>> + reg = <0 0x0aaf0000 0 0x10000>; >> >> 0x0, please. > > There's currently 80 cases of 0 and 20 of 0x0 in this file, is 0x0 > the preferred way nowadays? > > If so, shall I also change 0 to 0x0 for reg in a separate patch? I'd say, yes, please, if Bjorn / Konrad do not object. > > Regards > Luca > >> >>> + clocks = <&gcc GCC_VIDEO_AHB_CLK>, >>> + <&rpmhcc RPMH_CXO_CLK>, >>> + <&sleep_clk>; >>> + clock-names = "iface", >>> + "bi_tcxo", >>> + "sleep_clk"; >>> + #clock-cells = <1>; >>> + #reset-cells = <1>; >>> + #power-domain-cells = <1>; >>> + }; >>> + >>> cci0: cci@ac4a000 { >>> compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; >>> reg = <0 0x0ac4a000 0 0x1000>; >>> >>> -- >>> 2.49.0 >>> > -- With best wishes Dmitry