From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8864D33B6D9; Tue, 3 Mar 2026 23:26:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772580399; cv=none; b=eD3xIb64viEQ2qrUMFwhA/oIhkm+F645eYpLbCNhuk/kgt4zHHcfaauUJg8vlN8o919q5Ia8Hh5FrW2xHM+ThrWOKdk1TyI+OUCvxFXKfFPTQkJrueZ7TWl7PzlGzeMgWEFeC/hf2kbgps/m68kom6KSqZcztTxb30571jizBYs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772580399; c=relaxed/simple; bh=nFeGYlARoMmzZtAGsU/X82xVpzi4kLYOlHaX8giYd9E=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=EPvE0aI6alHYDEQtjXO8sBU18SLamVpIP8Vzbx5zAt02AC4XATeMUZ9Wf1xFl28ZyTdrhcPMQjM6UTREsWDOtmsE16rNM5KczeXxFIENKu1q0pBCHHXb2BypaNs3DGHOlidZ+qrMt+xuLViSdlI4HqX9fyfeyqbn+GNpcM0Rn0E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n74hPDPB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n74hPDPB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D3BAC19422; Tue, 3 Mar 2026 23:26:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772580399; bh=nFeGYlARoMmzZtAGsU/X82xVpzi4kLYOlHaX8giYd9E=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=n74hPDPBnyDxll6kkWMhhUWFfbWcwH/8WRXLFMaUYgecR4gZlQ+dQw2VHF2ZhjNAa E9jLyiAa+ZjrDsvfh6sWHr4wyIfhVeKZ1zGPDiHa2FpJ4svToAB2X/fWKPhxgR3Nhq Uedh+3NceAhz4ZZrYetl8IyG86Utio2s2PVc74N1TE/hqLkj53OKVz6hQF2BJn2ZeF 49JvQOQCig0vJCeroodg9zmBnAc+rJVHCWFcoRWH1nO44vwImg5Pjh+dlWx8/HdJsP q0iKLAyAPld7Rl2zhZCYRGyOJkZd/oI3sdZXGePQub3DM9MpLJWtL0YgFWMuzxnsI7 GtsdiH/Gt5BsA== Message-ID: Date: Tue, 3 Mar 2026 23:26:33 +0000 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Vijay Kumar Tumati , Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong Cc: Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260226-x1e-csi2-phy-v3-0-11e608759410@linaro.org> <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org> <4pFL6wOeTKUt-Zq4YbjqJdacMgUIPSYJD-4-5DcIMEZ1sM7JsNFYcSv1bd7ZRVOklTsmkEfxM2b6tTflmiECNQ==@protonmail.internalid> <03b44922-72d5-465b-96e1-97a19655e97d@kernel.org> <4440a3a8-7281-4bea-bb84-7a9d19ef7ce9@oss.qualcomm.com> <2a1155bd-7dc5-4ed8-b1eb-ddfa483c75ca@oss.qualcomm.com> <4fea7117-ebd3-4279-9973-3ac4f2a78835@linaro.org> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/03/2026 23:17, Vijay Kumar Tumati wrote: > Sorry, I do not know about videocc. I think Iris does those itself see: iris: video-codec@aa00000 { compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris"; reg = <0 0x0aa00000 0 0xf0000>; interrupts = ; power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, <&videocc VIDEO_CC_MVS0_GDSC>, <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_MMCX>; power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; Still not getting an especially clear picture on what _levels_ you are proposing here for MXA - here are the three opps we have for the PHY. Sorry I don't get how turbo is coming into this .. + csiphy_opp_table: opp-table-csiphy { + compatible = "operating-points-v2"; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; --- bod