* [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback
2025-08-24 20:41 [PATCH 0/3] " Nickolay Goppen
@ 2025-08-24 20:41 ` Nickolay Goppen
0 siblings, 0 replies; 9+ messages in thread
From: Nickolay Goppen @ 2025-08-24 20:41 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, Nickolay Goppen
By default pin_offset is calculated by formula:
LPI_TLMM_REG_OFFSET * pin_id. However not all platforms are using this
pin_offset formula (e.g. SDM660 LPASS LPI uses a predefined array of
offsets [1]), so add a callback to the default pin_offset function to
add an ability for some platforms to use their own quirky pin_offset
functions and add callbacks to pin_offset_default function for other
platforms.
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 13 +++++++++++--
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 ++
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 1 +
11 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 57fefeb603f0e2502fccd14ba3982ae3cb591978..8ba0ebf12d8113cdc501e9fe97311ec0764fbef5 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -38,16 +38,25 @@ struct lpi_pinctrl {
const struct lpi_pinctrl_variant_data *data;
};
+u32 pin_offset_default(int pin_id)
+{
+ return LPI_TLMM_REG_OFFSET * pin_id;
+}
+
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr)
{
- return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+ const u32 pin_offset = state->data->pin_offset(pin);
+
+ return ioread32(state->tlmm_base + pin_offset + addr);
}
static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr, unsigned int val)
{
- iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+ const u32 pin_offset = state->data->pin_offset(pin);
+
+ iowrite32(val, state->tlmm_base + pin_offset + addr);
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..3a2969ac85410e9fb796ec792d1349822257b3a0 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -85,9 +85,11 @@ struct lpi_pinctrl_variant_data {
const struct lpi_function *functions;
int nfunctions;
unsigned int flags;
+ u32 (*pin_offset)(int pin_id);
};
int lpi_pinctrl_probe(struct platform_device *pdev);
void lpi_pinctrl_remove(struct platform_device *pdev);
+u32 pin_offset_default(int pin_id);
#endif /*__PINCTRL_LPASS_LPI_H__*/
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
index 1161f0a91a002aaa9b1ba2f9ca13e94b2f145ec8..ed0c57fb1ed4770cce4afe7b1f3ec51aa3d44cf3 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
.ngroups = ARRAY_SIZE(sc7280_groups),
.functions = sc7280_functions,
.nfunctions = ARRAY_SIZE(sc7280_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
index 0e839b6aaaf4bd88f078cf36091faa9c2c885518..40834242a7699352c63ad2ddc82ca3663a39275f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
@@ -162,6 +162,7 @@ static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = {
.ngroups = ARRAY_SIZE(sc8280xp_groups),
.functions = sc8280xp_functions,
.nfunctions = ARRAY_SIZE(sc8280xp_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
index c0e178be9cfc3ea8578a39d8998033058f40dabf..69074c80744663268fc034019ca5523a18ce7f22 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
@@ -213,6 +213,7 @@ static const struct lpi_pinctrl_variant_data sm4250_lpi_data = {
.ngroups = ARRAY_SIZE(sm4250_groups),
.functions = sm4250_functions,
.nfunctions = ARRAY_SIZE(sm4250_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
index b7d9186861a2ffa9f3c00a660bde00858fff9462..651e52f4c886821ebb8207af3783da87758f1a30 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
@@ -133,6 +133,7 @@ static const struct lpi_pinctrl_variant_data sm6115_lpi_data = {
.ngroups = ARRAY_SIZE(sm6115_groups),
.functions = sm6115_functions,
.nfunctions = ARRAY_SIZE(sm6115_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
index 64494a86490e2f5d3e00184622f68097bbcdfff0..a693df05c4fdb40750f449a58817e2371e564dea 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -123,6 +123,7 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi_data = {
.ngroups = ARRAY_SIZE(sm8250_groups),
.functions = sm8250_functions,
.nfunctions = ARRAY_SIZE(sm8250_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
index 7b146b4acfdf42e7dd69f1f022c0041b3e45b174..15d453482d68b8b9ae2d572f7538e05f83425a12 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
@@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sm8350_lpi_data = {
.ngroups = ARRAY_SIZE(sm8350_groups),
.functions = sm8350_functions,
.nfunctions = ARRAY_SIZE(sm8350_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
index 439f6541622e924a2a77db7a8b15ccb709e7a53d..629a110963d610fe7b9667ea1abab66338711bf1 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
@@ -191,6 +191,7 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi_data = {
.ngroups = ARRAY_SIZE(sm8450_groups),
.functions = sm8450_functions,
.nfunctions = ARRAY_SIZE(sm8450_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
index 73065919c8c2654670b07372bd2dd5839baf2979..1ebc93a61e965f8c0d29348586905cb0e38ae074 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
@@ -199,6 +199,7 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi_data = {
.ngroups = ARRAY_SIZE(sm8550_groups),
.functions = sm8550_functions,
.nfunctions = ARRAY_SIZE(sm8550_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
index f9fcedf5a65d7115e605c54229ba0096b9081636..a6dfeef0f6fa0860f44808a4bb8e5db57d10d116 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
@@ -206,6 +206,7 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi_data = {
.functions = sm8650_functions,
.nfunctions = ARRAY_SIZE(sm8650_functions),
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 0/3] Add SDM660 LPASS LPI TLMM
@ 2025-08-24 20:42 Nickolay Goppen
2025-08-24 20:42 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Nickolay Goppen @ 2025-08-24 20:42 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, Nickolay Goppen, Richard Acayan
This patch series adds SDM660 LPASS LPI TLMM pinctrl driver and
introduces pin_offset callback for LPI pinctrl drivers to support
SDM660's quirky pin_offset function which uses an array with
predefined offsets [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
---
Nickolay Goppen (2):
pinctrl: qcom: lpass-lpi: Introduce pin_offset callback
dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
Richard Acayan (1):
pinctrl: qcom: Add SDM660 LPASS LPI TLMM
.../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 74 ++++++++
drivers/pinctrl/qcom/Kconfig | 10 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 13 +-
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 +
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 196 +++++++++++++++++++++
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 1 +
15 files changed, 303 insertions(+), 2 deletions(-)
---
base-commit: 038d61fd642278bab63ee8ef722c50d10ab01e8f
change-id: 20250824-sdm660-lpass-lpi-a8b02a23861a
Best regards,
--
Nickolay Goppen <setotau@yandex.ru>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback
2025-08-24 20:42 [PATCH 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen
@ 2025-08-24 20:42 ` Nickolay Goppen
2025-08-24 23:24 ` kernel test robot
2025-08-25 9:37 ` Dmitry Baryshkov
2025-08-24 20:42 ` [PATCH 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen
2025-08-24 20:42 ` [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen
2 siblings, 2 replies; 9+ messages in thread
From: Nickolay Goppen @ 2025-08-24 20:42 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, Nickolay Goppen
By default pin_offset is calculated by formula:
LPI_TLMM_REG_OFFSET * pin_id. However not all platforms are using this
pin_offset formula (e.g. SDM660 LPASS LPI uses a predefined array of
offsets [1]), so add a callback to the default pin_offset function to
add an ability for some platforms to use their own quirky pin_offset
functions and add callbacks to pin_offset_default function for other
platforms.
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 13 +++++++++++--
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 ++
drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 1 +
drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 1 +
11 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 57fefeb603f0e2502fccd14ba3982ae3cb591978..8ba0ebf12d8113cdc501e9fe97311ec0764fbef5 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -38,16 +38,25 @@ struct lpi_pinctrl {
const struct lpi_pinctrl_variant_data *data;
};
+u32 pin_offset_default(int pin_id)
+{
+ return LPI_TLMM_REG_OFFSET * pin_id;
+}
+
static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr)
{
- return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+ const u32 pin_offset = state->data->pin_offset(pin);
+
+ return ioread32(state->tlmm_base + pin_offset + addr);
}
static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
unsigned int addr, unsigned int val)
{
- iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
+ const u32 pin_offset = state->data->pin_offset(pin);
+
+ iowrite32(val, state->tlmm_base + pin_offset + addr);
return 0;
}
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..3a2969ac85410e9fb796ec792d1349822257b3a0 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -85,9 +85,11 @@ struct lpi_pinctrl_variant_data {
const struct lpi_function *functions;
int nfunctions;
unsigned int flags;
+ u32 (*pin_offset)(int pin_id);
};
int lpi_pinctrl_probe(struct platform_device *pdev);
void lpi_pinctrl_remove(struct platform_device *pdev);
+u32 pin_offset_default(int pin_id);
#endif /*__PINCTRL_LPASS_LPI_H__*/
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
index 1161f0a91a002aaa9b1ba2f9ca13e94b2f145ec8..ed0c57fb1ed4770cce4afe7b1f3ec51aa3d44cf3 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
@@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
.ngroups = ARRAY_SIZE(sc7280_groups),
.functions = sc7280_functions,
.nfunctions = ARRAY_SIZE(sc7280_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
index 0e839b6aaaf4bd88f078cf36091faa9c2c885518..40834242a7699352c63ad2ddc82ca3663a39275f 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
@@ -162,6 +162,7 @@ static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = {
.ngroups = ARRAY_SIZE(sc8280xp_groups),
.functions = sc8280xp_functions,
.nfunctions = ARRAY_SIZE(sc8280xp_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
index c0e178be9cfc3ea8578a39d8998033058f40dabf..69074c80744663268fc034019ca5523a18ce7f22 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
@@ -213,6 +213,7 @@ static const struct lpi_pinctrl_variant_data sm4250_lpi_data = {
.ngroups = ARRAY_SIZE(sm4250_groups),
.functions = sm4250_functions,
.nfunctions = ARRAY_SIZE(sm4250_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
index b7d9186861a2ffa9f3c00a660bde00858fff9462..651e52f4c886821ebb8207af3783da87758f1a30 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
@@ -133,6 +133,7 @@ static const struct lpi_pinctrl_variant_data sm6115_lpi_data = {
.ngroups = ARRAY_SIZE(sm6115_groups),
.functions = sm6115_functions,
.nfunctions = ARRAY_SIZE(sm6115_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
index 64494a86490e2f5d3e00184622f68097bbcdfff0..a693df05c4fdb40750f449a58817e2371e564dea 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
@@ -123,6 +123,7 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi_data = {
.ngroups = ARRAY_SIZE(sm8250_groups),
.functions = sm8250_functions,
.nfunctions = ARRAY_SIZE(sm8250_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
index 7b146b4acfdf42e7dd69f1f022c0041b3e45b174..15d453482d68b8b9ae2d572f7538e05f83425a12 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
@@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sm8350_lpi_data = {
.ngroups = ARRAY_SIZE(sm8350_groups),
.functions = sm8350_functions,
.nfunctions = ARRAY_SIZE(sm8350_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
index 439f6541622e924a2a77db7a8b15ccb709e7a53d..629a110963d610fe7b9667ea1abab66338711bf1 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
@@ -191,6 +191,7 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi_data = {
.ngroups = ARRAY_SIZE(sm8450_groups),
.functions = sm8450_functions,
.nfunctions = ARRAY_SIZE(sm8450_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
index 73065919c8c2654670b07372bd2dd5839baf2979..1ebc93a61e965f8c0d29348586905cb0e38ae074 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
@@ -199,6 +199,7 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi_data = {
.ngroups = ARRAY_SIZE(sm8550_groups),
.functions = sm8550_functions,
.nfunctions = ARRAY_SIZE(sm8550_functions),
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
index f9fcedf5a65d7115e605c54229ba0096b9081636..a6dfeef0f6fa0860f44808a4bb8e5db57d10d116 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
@@ -206,6 +206,7 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi_data = {
.functions = sm8650_functions,
.nfunctions = ARRAY_SIZE(sm8650_functions),
.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
+ .pin_offset = pin_offset_default,
};
static const struct of_device_id lpi_pinctrl_of_match[] = {
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
2025-08-24 20:42 [PATCH 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen
2025-08-24 20:42 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
@ 2025-08-24 20:42 ` Nickolay Goppen
2025-08-24 20:42 ` [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen
2 siblings, 0 replies; 9+ messages in thread
From: Nickolay Goppen @ 2025-08-24 20:42 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, Nickolay Goppen, Richard Acayan
Add bindings for pin controller in SDM660 Low Power Audio SubSystem
(LPASS).
Co-developed-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
---
.../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 74 ++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..6b930a5b914bc79a00dbaead41189efc525c2eb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM660 SoC LPASS LPI TLMM
+
+maintainers:
+ - Nickolay Goppen <setotau@yandex.ru>
+
+description:
+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+ (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC.
+
+properties:
+ compatible:
+ const: qcom,sdm660-lpass-lpi-pinctrl
+
+ reg:
+ items:
+ - description: LPASS LPI TLMM Control and Status registers
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sdm660-lpass-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sdm660-lpass-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sdm660-lpass-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-9]|2[0-6])$"
+
+ function:
+ enum: [ gpio, comp_rx, dmic12, dmic34, mclk0, pdm_2_gpios,
+ pdm_clk, pdm_rx, pdm_sync ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+allOf:
+ - $ref: qcom,lpass-lpi-common.yaml#
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ lpi_tlmm: pinctrl@15070000 {
+ compatible = "qcom,sdm660-lpass-lpi-pinctrl";
+ reg = <0x15070000 0x20000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpi_tlmm 0 0 32>;
+ };
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM
2025-08-24 20:42 [PATCH 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen
2025-08-24 20:42 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
2025-08-24 20:42 ` [PATCH 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen
@ 2025-08-24 20:42 ` Nickolay Goppen
2025-08-25 9:48 ` Dmitry Baryshkov
2025-08-26 6:01 ` kernel test robot
2 siblings, 2 replies; 9+ messages in thread
From: Nickolay Goppen @ 2025-08-24 20:42 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, Nickolay Goppen, Richard Acayan
From: Richard Acayan <mailingradian@gmail.com>
The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.
Also, this driver uses it's own quirky pin_offset function like downstream
driver does [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
Co-developed-by: Nickolay Goppen <setotau@yandex.ru>
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
drivers/pinctrl/qcom/Kconfig | 10 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 196 ++++++++++++++++++++++++
3 files changed, 207 insertions(+)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index dd9bbe8f3e11c37418d2143b33c21eeea10d456b..ef42520115f461302098d878cb76c6f25e55b5e4 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -68,6 +68,16 @@ config PINCTRL_SC7280_LPASS_LPI
Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
+config PINCTRL_SDM660_LPASS_LPI
+ tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver"
+ depends on GPIOLIB
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_LPASS_LPI
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+ (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform.
+
config PINCTRL_SM4250_LPASS_LPI
tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 954f5291cc37242baffc021e3c68d850aabd57cd..cea8617ac650ecfc75c2a0c745a53d6a1b829842 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o
obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
+obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o
obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
new file mode 100644
index 0000000000000000000000000000000000000000..788e1c019b0b7a22360d8c32180b5abf4d0fc0dc
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * This driver is solely based on the limited information in downstream code.
+ * Any verification with schematics would be greatly appreciated.
+ *
+ * Copyright (c) 2023, Richard Acayan. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+ LPI_MUX_comp_rx,
+ LPI_MUX_dmic12,
+ LPI_MUX_dmic34,
+ LPI_MUX_mclk0,
+ LPI_MUX_pdm_2_gpios,
+ LPI_MUX_pdm_clk,
+ LPI_MUX_pdm_rx,
+ LPI_MUX_pdm_sync,
+
+ LPI_MUX_gpio,
+ LPI_MUX__,
+};
+
+static const u32 sdm660_lpi_offset[] = {
+ 0x00000000,
+ 0x00001000,
+ 0x00002000,
+ 0x00002010,
+ 0x00003000,
+ 0x00003010,
+ 0x00004000,
+ 0x00004010,
+ 0x00005000,
+ 0x00005010,
+ 0x00005020,
+ 0x00005030,
+ 0x00006000,
+ 0x00006010,
+ 0x00007000,
+ 0x00007010,
+ 0x00005040,
+ 0x00005050,
+ 0x00008000,
+ 0x00008010,
+ 0x00008020,
+ 0x00008030,
+ 0x00008040,
+ 0x00008050,
+ 0x00008060,
+ 0x00008070,
+ 0x00009000,
+ 0x00009010,
+ 0x0000A000,
+ 0x0000A010,
+ 0x0000B000,
+ 0x0000B010,
+};
+
+static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+ PINCTRL_PIN(15, "gpio15"),
+ PINCTRL_PIN(16, "gpio16"),
+ PINCTRL_PIN(17, "gpio17"),
+ PINCTRL_PIN(18, "gpio18"),
+ PINCTRL_PIN(19, "gpio19"),
+ PINCTRL_PIN(20, "gpio20"),
+ PINCTRL_PIN(21, "gpio21"),
+ PINCTRL_PIN(22, "gpio22"),
+ PINCTRL_PIN(23, "gpio23"),
+ PINCTRL_PIN(24, "gpio24"),
+ PINCTRL_PIN(25, "gpio25"),
+ PINCTRL_PIN(26, "gpio26"),
+ PINCTRL_PIN(27, "gpio27"),
+ PINCTRL_PIN(28, "gpio28"),
+ PINCTRL_PIN(29, "gpio29"),
+ PINCTRL_PIN(30, "gpio30"),
+ PINCTRL_PIN(31, "gpio31"),
+};
+
+static const char * const comp_rx_groups[] = { "gpio22", "gpio24" };
+static const char * const dmic12_groups[] = { "gpio26", "gpio28" };
+static const char * const dmic34_groups[] = { "gpio27", "gpio29" };
+static const char * const mclk0_groups[] = { "gpio18" };
+static const char * const pdm_2_gpios_groups[] = { "gpio20" };
+static const char * const pdm_clk_groups[] = { "gpio18" };
+static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" };
+static const char * const pdm_sync_groups[] = { "gpio19" };
+
+const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = {
+ LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(8, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(9, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(11, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
+
+ /* The function names of the PDM GPIOs are derived from SDM670 */
+ LPI_PINGROUP(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _),
+ LPI_PINGROUP(19, LPI_NO_SLEW, pdm_sync, _, _, _),
+ LPI_PINGROUP(20, LPI_NO_SLEW, pdm_2_gpios, _, _, _),
+ LPI_PINGROUP(21, LPI_NO_SLEW, pdm_rx, _, _, _),
+ LPI_PINGROUP(22, LPI_NO_SLEW, comp_rx, _, _, _),
+ LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _),
+ LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _),
+ LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _),
+ LPI_PINGROUP(26, LPI_NO_SLEW, dmic12, _, _, _),
+ LPI_PINGROUP(27, LPI_NO_SLEW, dmic34, _, _, _),
+ LPI_PINGROUP(28, LPI_NO_SLEW, dmic12, _, _, _),
+ LPI_PINGROUP(29, LPI_NO_SLEW, dmic34, _, _, _),
+
+ LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _),
+ LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _),
+};
+
+const struct lpi_function sdm660_lpi_pinctrl_functions[] = {
+ LPI_FUNCTION(comp_rx),
+ LPI_FUNCTION(dmic12),
+ LPI_FUNCTION(dmic34),
+ LPI_FUNCTION(mclk0),
+ LPI_FUNCTION(pdm_2_gpios),
+ LPI_FUNCTION(pdm_clk),
+ LPI_FUNCTION(pdm_rx),
+ LPI_FUNCTION(pdm_sync),
+};
+
+static u32 pin_offset_sdm660(int pin_id)
+{
+ return sdm660_lpi_offset[pin_id];
+}
+
+static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data = {
+ .pins = sdm660_lpi_pinctrl_pins,
+ .npins = ARRAY_SIZE(sdm660_lpi_pinctrl_pins),
+ .groups = sdm660_lpi_pinctrl_groups,
+ .ngroups = ARRAY_SIZE(sdm660_lpi_pinctrl_groups),
+ .functions = sdm660_lpi_pinctrl_functions,
+ .nfunctions = ARRAY_SIZE(sdm660_lpi_pinctrl_functions),
+ .flags = LPI_FLAG_SLEW_RATE_SAME_REG,
+ .pin_offset = pin_offset_sdm660,
+};
+
+static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = {
+ {
+ .compatible = "qcom,sdm660-lpass-lpi-pinctrl",
+ .data = &sdm660_lpi_pinctrl_data,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match);
+
+static struct platform_driver sdm660_lpi_pinctrl_driver = {
+ .driver = {
+ .name = "qcom-sdm660-lpass-lpi-pinctrl",
+ .of_match_table = sdm660_lpi_pinctrl_of_match,
+ },
+ .probe = lpi_pinctrl_probe,
+ .remove = lpi_pinctrl_remove,
+};
+module_platform_driver(sdm660_lpi_pinctrl_driver);
+
+MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>");
+MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
--
2.51.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback
2025-08-24 20:42 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
@ 2025-08-24 23:24 ` kernel test robot
2025-08-25 9:37 ` Dmitry Baryshkov
1 sibling, 0 replies; 9+ messages in thread
From: kernel test robot @ 2025-08-24 23:24 UTC (permalink / raw)
To: Nickolay Goppen, Bjorn Andersson, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: oe-kbuild-all, linux-arm-msm, linux-gpio, linux-kernel,
devicetree, ~postmarketos/upstreaming, Nickolay Goppen
Hi Nickolay,
kernel test robot noticed the following build errors:
[auto build test ERROR on 038d61fd642278bab63ee8ef722c50d10ab01e8f]
url: https://github.com/intel-lab-lkp/linux/commits/Nickolay-Goppen/pinctrl-qcom-lpass-lpi-Introduce-pin_offset-callback/20250825-045348
base: 038d61fd642278bab63ee8ef722c50d10ab01e8f
patch link: https://lore.kernel.org/r/20250824-sdm660-lpass-lpi-v1-1-003d5cc28234%40yandex.ru
patch subject: [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback
config: sh-randconfig-002-20250825 (https://download.01.org/0day-ci/archive/20250825/202508250651.QMqSAkyR-lkp@intel.com/config)
compiler: sh4-linux-gcc (GCC) 13.4.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250825/202508250651.QMqSAkyR-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508250651.QMqSAkyR-lkp@intel.com/
All errors (new ones prefixed by >>, old ones prefixed by <<):
>> ERROR: modpost: "pin_offset_default" [drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.ko] undefined!
>> ERROR: modpost: "pin_offset_default" [drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.ko] undefined!
>> ERROR: modpost: "pin_offset_default" [drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.ko] undefined!
>> ERROR: modpost: "pin_offset_default" [drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.ko] undefined!
>> ERROR: modpost: "pin_offset_default" [drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.ko] undefined!
>> ERROR: modpost: "pin_offset_default" [drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.ko] undefined!
ERROR: modpost: "devm_clk_hw_register" [drivers/media/i2c/tc358746.ko] undefined!
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback
2025-08-24 20:42 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
2025-08-24 23:24 ` kernel test robot
@ 2025-08-25 9:37 ` Dmitry Baryshkov
1 sibling, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2025-08-25 9:37 UTC (permalink / raw)
To: Nickolay Goppen
Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming
On Sun, Aug 24, 2025 at 11:42:23PM +0300, Nickolay Goppen wrote:
> By default pin_offset is calculated by formula:
> LPI_TLMM_REG_OFFSET * pin_id. However not all platforms are using this
> pin_offset formula (e.g. SDM660 LPASS LPI uses a predefined array of
> offsets [1]), so add a callback to the default pin_offset function to
> add an ability for some platforms to use their own quirky pin_offset
> functions and add callbacks to pin_offset_default function for other
> platforms.
>
> [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
>
> Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
> ---
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 13 +++++++++++--
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 ++
> drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 1 +
> drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 1 +
> 11 files changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> index 57fefeb603f0e2502fccd14ba3982ae3cb591978..8ba0ebf12d8113cdc501e9fe97311ec0764fbef5 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
> @@ -38,16 +38,25 @@ struct lpi_pinctrl {
> const struct lpi_pinctrl_variant_data *data;
> };
>
> +u32 pin_offset_default(int pin_id)
Please use the prefix that matches the rest of the functions in the
file: lpi_pinctlr_.
> +{
> + return LPI_TLMM_REG_OFFSET * pin_id;
> +}
Missing EXPORT_MODULE_GPL here. However it might be better to convert
this to a macro or static inline in the header and call it directly it
the driver doesn't define the callback.
> +
> static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
> unsigned int addr)
> {
> - return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
> + const u32 pin_offset = state->data->pin_offset(pin);
> +
> + return ioread32(state->tlmm_base + pin_offset + addr);
> }
>
> static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
> unsigned int addr, unsigned int val)
> {
> - iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
> + const u32 pin_offset = state->data->pin_offset(pin);
> +
> + iowrite32(val, state->tlmm_base + pin_offset + addr);
>
> return 0;
> }
> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..3a2969ac85410e9fb796ec792d1349822257b3a0 100644
> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
> @@ -85,9 +85,11 @@ struct lpi_pinctrl_variant_data {
> const struct lpi_function *functions;
> int nfunctions;
> unsigned int flags;
> + u32 (*pin_offset)(int pin_id);
> };
>
> int lpi_pinctrl_probe(struct platform_device *pdev);
> void lpi_pinctrl_remove(struct platform_device *pdev);
> +u32 pin_offset_default(int pin_id);
>
> #endif /*__PINCTRL_LPASS_LPI_H__*/
> diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> index 1161f0a91a002aaa9b1ba2f9ca13e94b2f145ec8..ed0c57fb1ed4770cce4afe7b1f3ec51aa3d44cf3 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c
> @@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi_data = {
> .ngroups = ARRAY_SIZE(sc7280_groups),
> .functions = sc7280_functions,
> .nfunctions = ARRAY_SIZE(sc7280_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
> index 0e839b6aaaf4bd88f078cf36091faa9c2c885518..40834242a7699352c63ad2ddc82ca3663a39275f 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c
> @@ -162,6 +162,7 @@ static const struct lpi_pinctrl_variant_data sc8280xp_lpi_data = {
> .ngroups = ARRAY_SIZE(sc8280xp_groups),
> .functions = sc8280xp_functions,
> .nfunctions = ARRAY_SIZE(sc8280xp_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
> index c0e178be9cfc3ea8578a39d8998033058f40dabf..69074c80744663268fc034019ca5523a18ce7f22 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
> @@ -213,6 +213,7 @@ static const struct lpi_pinctrl_variant_data sm4250_lpi_data = {
> .ngroups = ARRAY_SIZE(sm4250_groups),
> .functions = sm4250_functions,
> .nfunctions = ARRAY_SIZE(sm4250_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
> index b7d9186861a2ffa9f3c00a660bde00858fff9462..651e52f4c886821ebb8207af3783da87758f1a30 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c
> @@ -133,6 +133,7 @@ static const struct lpi_pinctrl_variant_data sm6115_lpi_data = {
> .ngroups = ARRAY_SIZE(sm6115_groups),
> .functions = sm6115_functions,
> .nfunctions = ARRAY_SIZE(sm6115_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> index 64494a86490e2f5d3e00184622f68097bbcdfff0..a693df05c4fdb40750f449a58817e2371e564dea 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c
> @@ -123,6 +123,7 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi_data = {
> .ngroups = ARRAY_SIZE(sm8250_groups),
> .functions = sm8250_functions,
> .nfunctions = ARRAY_SIZE(sm8250_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
> index 7b146b4acfdf42e7dd69f1f022c0041b3e45b174..15d453482d68b8b9ae2d572f7538e05f83425a12 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c
> @@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sm8350_lpi_data = {
> .ngroups = ARRAY_SIZE(sm8350_groups),
> .functions = sm8350_functions,
> .nfunctions = ARRAY_SIZE(sm8350_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
> index 439f6541622e924a2a77db7a8b15ccb709e7a53d..629a110963d610fe7b9667ea1abab66338711bf1 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c
> @@ -191,6 +191,7 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi_data = {
> .ngroups = ARRAY_SIZE(sm8450_groups),
> .functions = sm8450_functions,
> .nfunctions = ARRAY_SIZE(sm8450_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
> index 73065919c8c2654670b07372bd2dd5839baf2979..1ebc93a61e965f8c0d29348586905cb0e38ae074 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c
> @@ -199,6 +199,7 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi_data = {
> .ngroups = ARRAY_SIZE(sm8550_groups),
> .functions = sm8550_functions,
> .nfunctions = ARRAY_SIZE(sm8550_functions),
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
> index f9fcedf5a65d7115e605c54229ba0096b9081636..a6dfeef0f6fa0860f44808a4bb8e5db57d10d116 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c
> @@ -206,6 +206,7 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi_data = {
> .functions = sm8650_functions,
> .nfunctions = ARRAY_SIZE(sm8650_functions),
> .flags = LPI_FLAG_SLEW_RATE_SAME_REG,
> + .pin_offset = pin_offset_default,
> };
>
> static const struct of_device_id lpi_pinctrl_of_match[] = {
>
> --
> 2.51.0
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM
2025-08-24 20:42 ` [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen
@ 2025-08-25 9:48 ` Dmitry Baryshkov
2025-08-26 6:01 ` kernel test robot
1 sibling, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2025-08-25 9:48 UTC (permalink / raw)
To: Nickolay Goppen
Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, Richard Acayan
On Sun, Aug 24, 2025 at 11:42:25PM +0300, Nickolay Goppen wrote:
> From: Richard Acayan <mailingradian@gmail.com>
>
> The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring
> pins related to audio. Add the driver for this.
> Also, this driver uses it's own quirky pin_offset function like downstream
> driver does [1].
>
> [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
>
> Co-developed-by: Nickolay Goppen <setotau@yandex.ru>
> Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
> drivers/pinctrl/qcom/Kconfig | 10 ++
> drivers/pinctrl/qcom/Makefile | 1 +
> drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 196 ++++++++++++++++++++++++
> 3 files changed, 207 insertions(+)
>
> +
> + 0x0000A000,
> + 0x0000A010,
> + 0x0000B000,
> + 0x0000B010,
Please lowercase the hex. LGTM otherwise.
> +};
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM
2025-08-24 20:42 ` [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen
2025-08-25 9:48 ` Dmitry Baryshkov
@ 2025-08-26 6:01 ` kernel test robot
1 sibling, 0 replies; 9+ messages in thread
From: kernel test robot @ 2025-08-26 6:01 UTC (permalink / raw)
To: Nickolay Goppen, Bjorn Andersson, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: oe-kbuild-all, linux-arm-msm, linux-gpio, linux-kernel,
devicetree, ~postmarketos/upstreaming, Nickolay Goppen,
Richard Acayan
Hi Nickolay,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 038d61fd642278bab63ee8ef722c50d10ab01e8f]
url: https://github.com/intel-lab-lkp/linux/commits/Nickolay-Goppen/pinctrl-qcom-lpass-lpi-Introduce-pin_offset-callback/20250825-045348
base: 038d61fd642278bab63ee8ef722c50d10ab01e8f
patch link: https://lore.kernel.org/r/20250824-sdm660-lpass-lpi-v1-3-003d5cc28234%40yandex.ru
patch subject: [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM
config: microblaze-randconfig-r123-20250826 (https://download.01.org/0day-ci/archive/20250826/202508261333.8hcdJOVB-lkp@intel.com/config)
compiler: microblaze-linux-gcc (GCC) 9.5.0
reproduce: (https://download.01.org/0day-ci/archive/20250826/202508261333.8hcdJOVB-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508261333.8hcdJOVB-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c:110:27: sparse: sparse: symbol 'sdm660_lpi_pinctrl_groups' was not declared. Should it be static?
>> drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c:148:27: sparse: sparse: symbol 'sdm660_lpi_pinctrl_functions' was not declared. Should it be static?
vim +/sdm660_lpi_pinctrl_groups +110 drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c
109
> 110 const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = {
111 LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
112 LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
113 LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
114 LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
115 LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
116 LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
117 LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
118 LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
119 LPI_PINGROUP(8, LPI_NO_SLEW, _, _, _, _),
120 LPI_PINGROUP(9, LPI_NO_SLEW, _, _, _, _),
121 LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, _),
122 LPI_PINGROUP(11, LPI_NO_SLEW, _, _, _, _),
123 LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
124 LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
125 LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
126 LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
127 LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
128 LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
129
130 /* The function names of the PDM GPIOs are derived from SDM670 */
131 LPI_PINGROUP(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _),
132 LPI_PINGROUP(19, LPI_NO_SLEW, pdm_sync, _, _, _),
133 LPI_PINGROUP(20, LPI_NO_SLEW, pdm_2_gpios, _, _, _),
134 LPI_PINGROUP(21, LPI_NO_SLEW, pdm_rx, _, _, _),
135 LPI_PINGROUP(22, LPI_NO_SLEW, comp_rx, _, _, _),
136 LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _),
137 LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _),
138 LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _),
139 LPI_PINGROUP(26, LPI_NO_SLEW, dmic12, _, _, _),
140 LPI_PINGROUP(27, LPI_NO_SLEW, dmic34, _, _, _),
141 LPI_PINGROUP(28, LPI_NO_SLEW, dmic12, _, _, _),
142 LPI_PINGROUP(29, LPI_NO_SLEW, dmic34, _, _, _),
143
144 LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _),
145 LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _),
146 };
147
> 148 const struct lpi_function sdm660_lpi_pinctrl_functions[] = {
149 LPI_FUNCTION(comp_rx),
150 LPI_FUNCTION(dmic12),
151 LPI_FUNCTION(dmic34),
152 LPI_FUNCTION(mclk0),
153 LPI_FUNCTION(pdm_2_gpios),
154 LPI_FUNCTION(pdm_clk),
155 LPI_FUNCTION(pdm_rx),
156 LPI_FUNCTION(pdm_sync),
157 };
158
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-08-26 6:02 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2025-08-24 20:42 [PATCH 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen
2025-08-24 20:42 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
2025-08-24 23:24 ` kernel test robot
2025-08-25 9:37 ` Dmitry Baryshkov
2025-08-24 20:42 ` [PATCH 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen
2025-08-24 20:42 ` [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen
2025-08-25 9:48 ` Dmitry Baryshkov
2025-08-26 6:01 ` kernel test robot
-- strict thread matches above, loose matches on Subject: below --
2025-08-24 20:41 [PATCH 0/3] " Nickolay Goppen
2025-08-24 20:41 ` [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Nickolay Goppen
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