From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>,
andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com,
mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org,
kishon@kernel.org, neil.armstrong@linaro.org,
abel.vesa@linaro.org, kw@linux.com
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com,
quic_krichai@quicinc.com, quic_vbadigan@quicinc.com
Subject: Re: [PATCH v1 1/4] arm64: dts: qcom: Add PCIe 5 support for HAMOA-IOT-SOM platform
Date: Tue, 14 Oct 2025 11:09:08 +0530 [thread overview]
Message-ID: <e146e351-ec42-4980-b41e-56bfd7dcc0fd@oss.qualcomm.com> (raw)
In-Reply-To: <20250922075509.3288419-2-ziyue.zhang@oss.qualcomm.com>
On 9/22/2025 1:25 PM, Ziyue Zhang wrote:
> Update the HAMOA-IOT-SOM device tree to enable PCIe 5 support. Add perst
> wake and clkreq sideband signals and required regulators in PCIe5
> controller and PHY device tree node.
>
> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Reviewed-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
- Krishna Chaitanya.
> ---
> arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 40 +++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
> index 1aead50b8920..0c8ae34c1f37 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi
> @@ -407,6 +407,23 @@ &pcie4_phy {
> status = "okay";
> };
>
> +&pcie5 {
> + perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
> +
> + pinctrl-0 = <&pcie5_default>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> +};
> +
> +&pcie5_phy {
> + vdda-phy-supply = <&vreg_l3i_0p8>;
> + vdda-pll-supply = <&vreg_l3e_1p2>;
> +
> + status = "okay";
> +};
> +
> &pcie6a {
> perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> @@ -477,6 +494,29 @@ wake-n-pins {
> };
> };
>
> + pcie5_default: pcie5-default-state {
> + clkreq-n-pins {
> + pins = "gpio150";
> + function = "pcie5_clk";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio149";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + wake-n-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> pcie6a_default: pcie6a-default-state {
> clkreq-n-pins {
> pins = "gpio153";
next prev parent reply other threads:[~2025-10-14 5:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-22 7:55 [PATCH v1 0/4] Add PCIe3 and PCIe5 support for HAMOA-IOT-EVK board Ziyue Zhang
2025-09-22 7:55 ` [PATCH v1 1/4] arm64: dts: qcom: Add PCIe 5 support for HAMOA-IOT-SOM platform Ziyue Zhang
2025-10-14 5:39 ` Krishna Chaitanya Chundru [this message]
2025-09-22 7:55 ` [PATCH v1 2/4] arm64: dts: qcom: Add PCIe 5 wwan regulator for HAMOA-IOT-EVK board Ziyue Zhang
2025-10-14 5:41 ` Krishna Chaitanya Chundru
2025-09-22 7:55 ` [PATCH v1 3/4] arm64: dts: qcom: Add PCIe 3 support for HAMOA-IOT-SOM platform Ziyue Zhang
2025-10-14 5:43 ` Krishna Chaitanya Chundru
2025-10-27 15:57 ` Bjorn Andersson
2025-09-22 7:55 ` [PATCH v1 4/4] arm64: dts: qcom: Add PCIe 3 regulators for HAMOA-IOT-EVK board Ziyue Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e146e351-ec42-4980-b41e-56bfd7dcc0fd@oss.qualcomm.com \
--to=krishna.chundru@oss.qualcomm.com \
--cc=abel.vesa@linaro.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jingoohan1@gmail.com \
--cc=johan+linaro@kernel.org \
--cc=kishon@kernel.org \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=kwilczynski@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=qiang.yu@oss.qualcomm.com \
--cc=quic_krichai@quicinc.com \
--cc=quic_vbadigan@quicinc.com \
--cc=robh@kernel.org \
--cc=vkoul@kernel.org \
--cc=ziyue.zhang@oss.qualcomm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox