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Mon, 28 Oct 2024 02:54:00 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49S2rxgZ023044 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2024 02:53:59 GMT Received: from [10.64.68.153] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 27 Oct 2024 19:53:55 -0700 Message-ID: Date: Mon, 28 Oct 2024 10:53:52 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: Add coresight nodes for QCS615 From: Jie Gan To: Konrad Dybcio , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , Tingwei Zhang , Jinlong Mao , Tao Zhang References: <20241017030005.893203-1-quic_jiegan@quicinc.com> <69be09ec-e9a5-4fb6-890e-74a65f3ce404@oss.qualcomm.com> <3f90b3d6-9637-47b7-ad8a-ff43cb28ad32@quicinc.com> Content-Language: en-US In-Reply-To: <3f90b3d6-9637-47b7-ad8a-ff43cb28ad32@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: G65cGfCj_fY372rmIK411cIbN-yhb_Yz X-Proofpoint-ORIG-GUID: G65cGfCj_fY372rmIK411cIbN-yhb_Yz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410280023 On 10/28/2024 8:54 AM, Jie Gan wrote: > > > On 10/26/2024 2:47 AM, Konrad Dybcio wrote: >> On 17.10.2024 5:00 AM, Jie Gan wrote: >>> Add following coresight components on QCS615, EUD, TMC/ETF, TPDM, >>> dynamic >>> Funnel, TPDA, Replicator and ETM. >>> >>> Signed-off-by: Jie Gan >>> --- >>> Already checked by command:dtbs_check W=1. >>> >>> Dependencies: >>> 1. Depends on qcs615 base dtsi change: >>> https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615- >>> v3-5-e37617e91c62@quicinc.com/ >>> 2. Depends on qcs615 AOSS_QMP change: >>> https://lore.kernel.org/linux-arm-msm/20241017025313.2028120-4- >>> quic_chunkaid@quicinc.com/ >>> --- >>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 1632 ++++++++++++++++++++++++++ >>>   1 file changed, 1632 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/ >>> dts/qcom/qcs615.dtsi >>> index 856b40e20cf3..87cca5de018e 100644 >>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>> @@ -202,6 +202,18 @@ l3_0: l3-cache { >>>           }; >>>       }; >>> +    dummy_eud: dummy_sink { >> >> Node names (after the ':' and before the '{' signs) can't contain >> underscores, use '-' instead. > Sure, will fix it. > >> >> [...] >> >>> +        stm@6002000 { >>> +            compatible = "arm,coresight-stm", "arm,primecell"; >>> +            reg = <0x0 0x6002000 0x0 0x1000>, >> >> Please pad the non-zero address part to 8 hex digits with leading >> zeroes, across the board > Will fix it. > >> >> This looks like a lot of nodes, all enabled by default. Will this run >> on a production-fused device? > Yes, usually Coresight nodes are enabled by default. Those nodes can run > on the commercial devices. Sorry, my last clarification is not clearly. The Coresight nodes are enabled by default for commercial devices(fused), but only part of functions can run with commercial devices because it needs check fuse data before running. If we want enable all debug functions related to coresight nodes on commercial devices, we need APDP override(APPS debug policy override) procedure first. The APDP override procedure will override some fuse data to allow debug sessions. Thanks, Jie