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Wed, 05 Nov 2025 21:00:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IFoZvD3PSRV3YeZCJj9DTySpLI8Sq4of4sBAy+31LPEveUTKkYFf/liRbgSaGeyzkkY9H6wag== X-Received: by 2002:a05:6a21:3294:b0:341:a18c:dd80 with SMTP id adf61e73a8af0-34f839e02cdmr8281525637.4.1762405250453; Wed, 05 Nov 2025 21:00:50 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-341d098fdd7sm540915a91.0.2025.11.05.21.00.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Nov 2025 21:00:50 -0800 (PST) Message-ID: Date: Thu, 6 Nov 2025 10:30:44 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: qcom: Program correct T_POWER_ON value for L1.2 exit timing To: Bjorn Helgaas Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com, quic_vbadigan@quicinc.com References: <20251104175657.GA1861670@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20251104175657.GA1861670@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: 2UGsClXt4L1JWJbuuX5-CHXs2Ko7Ede0 X-Proofpoint-GUID: 2UGsClXt4L1JWJbuuX5-CHXs2Ko7Ede0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA2MDAzNyBTYWx0ZWRfX0XvsPqZEkfgu ZRZf9v9AakYwuC5BsmpsBhPATo4ZlA3bVNzHOGYgEOT2XqDAZEayiClU378pntii3e44EiMkE92 JuuKJDgmUzmsoZBQ73sS4fSmxmWFuu4scS4+gK2AP36a77ud1+NCS5Uev+yVbHENVgw7a+NrA94 w0kGF1MY/FAd/8cGQmDqKLyJd/sMawapUC/yTmtik9VALD+GkQcgadggY3hnB3aNpIg1UVy/r64 5Gadvgrc47liLaykQ8aTAFGq2M2wAOdYtf9dDyexoi2VcZ0/OsJeoE9hC7M/HotOATjB08PDcfk G2FMK+Yk4QqDeC6XhpCC/VJx/+tkmEDK5bUDaCp3Ix9XUmUfaFJePqbII6B8xGeCO73VnGnVz7D D2esvk/iAEKMVQQz+kd0EEZuI7j7JA== X-Authority-Analysis: v=2.4 cv=Mdhhep/f c=1 sm=1 tr=0 ts=690c2b83 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=wBt9fhMRhOodALO6grUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-05_09,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 spamscore=0 clxscore=1015 malwarescore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511060037 On 11/4/2025 11:26 PM, Bjorn Helgaas wrote: > On Tue, Nov 04, 2025 at 05:42:45PM +0530, Krishna Chaitanya Chundru wrote: >> The T_POWER_ON indicates the time (in μs) that a Port requires the port >> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ# >> asserted before actively driving the interface. This value is used by >> the ASPM driver to compute the LTR_L1.2_THRESHOLD. >> >> Currently, the root port exposes a T_POWER_ON value of zero in the L1SS >> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations. >> This can result in improper L1.2 exit behavior and can trigger AER's. >> >> To address this, program the T_POWER_ON value to 80us (scale = 1, >> value = 8) in the PCI_L1SS_CAP register during host initialization. This >> ensures that ASPM can take the root port's T_POWER_ON value into account >> while calculating the LTR_L1.2_THRESHOLD value. > I think the question is whether the value depends on the circuit > design of a particular platform (and should therefore come from DT), > or whether it depends solely on the qcom device. Yes it depends on design. > PCIe r7.0, sec 5.5.4, says: > > The T_POWER_ON and Common_Mode_Restore_Time fields must be > programmed to the appropriate values based on the components and AC > coupling capacitors used in the connection linking the two > components. The determination of these values is design > implementation specific. > > That suggests to me that maybe there should be devicetree properties > related to these. Obviously these would not be qcom-specific since > this is standard PCIe stuff. Yes Bjorn these are PCIe stuff only, I can go to Device tree route if we have different values for each target, as of now we are using this same value in all targets as recommended by our HW team. If there is at least one more target or one more vendor who needs to program this we can take devicetree property route. I am ok to go with devicetree way also if you insists. - Krishna Chaitanya. > Use "μs" or "us" consistently; there's a mix above. > >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-qcom.c | 23 +++++++++++++++++++++++ >> 1 file changed, 23 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index c48a20602d7fa4c50056ccf6502d3b5bf0a8287f..52a3412bd2584c8bf5d281fa6a0ed22141ad1989 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1252,6 +1252,27 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci) >> return val & PCI_EXP_LNKSTA_DLLLA; >> } >> >> +static void qcom_pcie_program_t_pwr_on(struct dw_pcie *pci) >> +{ >> + u16 offset; >> + u32 val; >> + >> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); >> + if (offset) { >> + dw_pcie_dbi_ro_wr_en(pci); >> + >> + val = readl(pci->dbi_base + offset + PCI_L1SS_CAP); >> + /* Program T power ON value to 80us */ >> + val &= ~(PCI_L1SS_CAP_P_PWR_ON_SCALE | PCI_L1SS_CAP_P_PWR_ON_VALUE); >> + val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_SCALE, 1); >> + val |= FIELD_PREP(PCI_L1SS_CAP_P_PWR_ON_VALUE, 8); >> + >> + writel(val, pci->dbi_base + offset + PCI_L1SS_CAP); >> + >> + dw_pcie_dbi_ro_wr_dis(pci); >> + } >> +} >> + >> static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) >> { >> struct qcom_pcie_port *port; >> @@ -1302,6 +1323,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) >> goto err_disable_phy; >> } >> >> + qcom_pcie_program_t_pwr_on(pci); >> + >> qcom_ep_reset_deassert(pcie); >> >> if (pcie->cfg->ops->config_sid) { >> >> --- >> base-commit: c9cfc122f03711a5124b4aafab3211cf4d35a2ac >> change-id: 20251104-t_power_on_fux-70dc68377941 >> >> Best regards, >> -- >> Krishna Chaitanya Chundru >>