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From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jingoo Han" <jingoohan1@gmail.com>,
	linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, mayank.rana@oss.qualcomm.com,
	quic_vbadigan@quicinc.com
Subject: Re: [PATCH v2 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields
Date: Tue, 24 Feb 2026 10:51:10 +0530	[thread overview]
Message-ID: <e5296567-db3a-48d1-b40b-2791ccf5d911@oss.qualcomm.com> (raw)
In-Reply-To: <20260223152901.GA3694918@bhelgaas>



On 2/23/2026 8:59 PM, Bjorn Helgaas wrote:
> On Mon, Feb 23, 2026 at 04:43:30PM +0530, Krishna Chaitanya Chundru wrote:
>> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON
>> parameter into the T_POWER_ON_Scale and T_POWER_ON_Value fields.
>>
>> This helper can be used by the controller drivers to change the
>> default/wrong value of T_POWER_ON in L1ss capability register to
>> avoid incorrect calculation of LTR_L1.2_THRESHOLD value.
>>
>> The helper converts a T_POWER_ON time specified in microseconds into
>> the appropriate scale/value encoding defined by the PCIe spec r7.0,
>> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped
>> to the largest representable encoding.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>> ---
>>   drivers/pci/pcie/aspm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>>   include/linux/pci.h     |  2 ++
>>   2 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
>> index 21f5d23e0b61bd7e1163cc869fe9356d1ab87b34..d7f9ae9e48c25dbc2d9b4887e2f74623688098e0 100644
>> --- a/drivers/pci/pcie/aspm.c
>> +++ b/drivers/pci/pcie/aspm.c
>> @@ -525,6 +525,49 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
>>   	return 0;
>>   }
>>   
>> +/**
>> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields
>> + * @t_power_on_us: T_POWER_ON time in microseconds
>> + * @scale: Encoded T_POWER_ON_Scale (0..2)
>> + * @value: Encoded T_POWER_ON_Value
>> + *
>> + * T_POWER_ON is encoded as:
>> + *   T_POWER_ON(us) = scale_unit(us) * value
>> + *
>> + * where scale_unit is selected by @scale:
>> + *   0: 2us
>> + *   1: 10us
>> + *   2: 100us
>> + *
>> + * If @t_power_on_us exceeds the maximum representable value, the result
>> + * is clamped to the largest encodable T_POWER_ON.
>> + *
>> + * See PCIe r7.0, sec 7.8.3.2.
>> + */
>> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value)
>> +{
>> +	u8 maxv = FIELD_MAX(PCI_L1SS_CTL2_T_PWR_ON_VALUE);
>> +
>> +	/*
>> +	 * T_POWER_ON_Value ("value") is a 5-bit field with max
>> +	 * value of 31.
>> +	 */
>> +	if (t_power_on_us <= 2 * maxv) {
>> +		*scale = 0; /* Value times 2us */
>> +		*value = DIV_ROUND_UP(t_power_on_us, 2);
>> +	} else if (t_power_on_us <= 10 * maxv) {
>> +		*scale = 1; /* Value times 10us */
>> +		*value = DIV_ROUND_UP(t_power_on_us, 10);
>> +	} else if (t_power_on_us <= 100 * maxv) {
>> +		*scale = 2; /* value times 100us */
>> +		*value = DIV_ROUND_UP(t_power_on_us, 100);
>> +	} else {
>> +		*scale = 2;
>> +		*value = maxv;
>> +	}
>> +}
>> +EXPORT_SYMBOL(pcie_encode_t_power_on);
>> +
>>   /*
>>    * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
>>    * register.  Ports enter L1.2 when the most recent LTR value is greater
>> diff --git a/include/linux/pci.h b/include/linux/pci.h
>> index 1c270f1d512301de4d462fe7e5097c32af5c6f8d..eec16fdcb9996ab0f663f4587a2367a676a49ce6 100644
>> --- a/include/linux/pci.h
>> +++ b/include/linux/pci.h
>> @@ -1911,6 +1911,7 @@ int pci_enable_link_state_locked(struct pci_dev *pdev, int state);
>>   void pcie_no_aspm(void);
>>   bool pcie_aspm_support_enabled(void);
>>   bool pcie_aspm_enabled(struct pci_dev *pdev);
>> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value);
> This looks like it should go in drivers/pci/pci.h.  I don't think it's
> needed outside drivers/pci/.
ack, I will fix in next patch.

- Krishna Chaitanya.
>>   #else
>>   static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
>>   { return 0; }
>> @@ -1923,6 +1924,7 @@ static inline int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
>>   static inline void pcie_no_aspm(void) { }
>>   static inline bool pcie_aspm_support_enabled(void) { return false; }
>>   static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
>> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) { }
>>   #endif
>>   
>>   #ifdef CONFIG_HOTPLUG_PCI
>>
>> -- 
>> 2.34.1
>>


  reply	other threads:[~2026-02-24  5:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-23 11:13 [PATCH v2 0/3] PCI: qcom: Program T_POWER_ON value for L1.2 exit timing Krishna Chaitanya Chundru
2026-02-23 11:13 ` [PATCH v2 1/3] PCI/ASPM: Add helper to encode L1SS T_POWER_ON fields Krishna Chaitanya Chundru
2026-02-23 15:29   ` Bjorn Helgaas
2026-02-24  5:21     ` Krishna Chaitanya Chundru [this message]
2026-02-23 11:13 ` [PATCH v2 2/3] PCI: dwc: Add helper to Program T_POWER_ON Krishna Chaitanya Chundru
2026-02-23 15:38   ` Bjorn Helgaas
2026-02-24  5:21     ` Krishna Chaitanya Chundru
2026-02-23 23:33   ` kernel test robot
2026-02-23 11:13 ` [PATCH v2 3/3] PCI: qcom: " Krishna Chaitanya Chundru
2026-02-23 13:57   ` Shawn Lin
2026-02-24  5:33     ` Krishna Chaitanya Chundru
2026-02-23 15:47   ` Bjorn Helgaas

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