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Date: Tue, 17 Sep 2024 15:47:09 +0200
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Subject: Re: [PATCH] drm/msm/a6xx+: Insert a fence wait before SMMU table
 update
To: Rob Clark <robdclark@gmail.com>, dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
 Akhil P Oommen <quic_akhilpo@quicinc.com>,
 Connor Abbott <cwabbott0@gmail.com>, Rob Clark <robdclark@chromium.org>,
 Sean Paul <sean@poorly.run>, Konrad Dybcio <konradybcio@kernel.org>,
 Abhinav Kumar <quic_abhinavk@quicinc.com>,
 Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
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 David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
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References: <20240913195132.8282-1-robdclark@gmail.com>
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From: Konrad Dybcio <konradybcio@kernel.org>
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On 13.09.2024 9:51 PM, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> The CP_SMMU_TABLE_UPDATE _should_ be waiting for idle, but on some
> devices (x1-85, possibly others), it seems to pass that barrier while
> there are still things in the event completion FIFO waiting to be
> written back to memory.

Can we try to force-fault around here on other GPUs and perhaps
limit this workaround?

Akhil, do we have any insight on this?

Konrad