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([2a01:e0a:982:cbb0:ed47:520d:3d5c:3acf]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432da2946a3sm157868985e9.35.2024.11.18.05.42.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Nov 2024 05:42:59 -0800 (PST) Message-ID: Date: Mon, 18 Nov 2024 14:42:58 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH RFC 6/8] drm/msm: adreno: enable GMU bandwidth for A740 and A750 To: Dmitry Baryshkov Cc: Akhil P Oommen , Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Connor Abbott , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org References: <20241113-topic-sm8x50-gpu-bw-vote-v1-0-3b8d39737a9b@linaro.org> <20241113-topic-sm8x50-gpu-bw-vote-v1-6-3b8d39737a9b@linaro.org> <8df952a8-3599-4198-9ff0-f7fac6d5feaf@linaro.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 15/11/2024 15:39, Dmitry Baryshkov wrote: > On Fri, Nov 15, 2024 at 10:20:01AM +0100, Neil Armstrong wrote: >> On 15/11/2024 08:33, Dmitry Baryshkov wrote: >>> On Wed, Nov 13, 2024 at 04:48:32PM +0100, Neil Armstrong wrote: >>>> Now all the DDR bandwidth voting via the GPU Management Unit (GMU) >>>> is in place, let's declare the Bus Control Modules (BCMs) and >>> >>> s/let's //g >>> >>>> it's parameters in the GPU info struct and add the GMU_BW_VOTE >>>> quirk to enable it. >>> >>> Can we define a function that checks for info.bcm[0].name isntead of >>> adding a quirk? >> >> Probably, I'll need ideas to how design this better, perhaps a simple >> capability bitfield in a6xx_info ? > > I'm not sure if I follow the question. I think it's better to check for > the presens of the data rather than having a separate 'cap' bit in > addition to that data. I don't fully agree here, I just follow the other features (CACHED_COHERENT/APRIV/...) nothing fancy. I'll introduce a features bitfield, so we don't mix them with quirks > >> There's other feature that are lacking, like ACD or BCL which are not supported >> on all a6xx/a7xx gpus. > > Akhil is currently working on ACD, as you have seen from the patches. Yep I've tested and reviewed the patches > >> >>> >>>> >>>> Signed-off-by: Neil Armstrong >>>> --- >>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 26 ++++++++++++++++++++++++-- >>>> 1 file changed, 24 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..014a24256b832d8e03fe06a6516b5348a5c0474a 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> @@ -1379,7 +1379,8 @@ static const struct adreno_info a7xx_gpus[] = { >>>> .inactive_period = DRM_MSM_INACTIVE_PERIOD, >>>> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | >>>> ADRENO_QUIRK_HAS_HW_APRIV | >>>> - ADRENO_QUIRK_PREEMPTION, >>>> + ADRENO_QUIRK_PREEMPTION | >>>> + ADRENO_QUIRK_GMU_BW_VOTE, >>>> .init = a6xx_gpu_init, >>>> .zapfw = "a740_zap.mdt", >>>> .a6xx = &(const struct a6xx_info) { >>>> @@ -1388,6 +1389,16 @@ static const struct adreno_info a7xx_gpus[] = { >>>> .pwrup_reglist = &a7xx_pwrup_reglist, >>>> .gmu_chipid = 0x7020100, >>>> .gmu_cgc_mode = 0x00020202, >>>> + .bcm = { >>>> + [0] = { .name = "SH0", .buswidth = 16 }, >>>> + [1] = { .name = "MC0", .buswidth = 4 }, >>>> + [2] = { >>>> + .name = "ACV", >>>> + .fixed = true, >>>> + .perfmode = BIT(3), >>>> + .perfmode_bw = 16500000, >>> >>> Is it a platform property or GPU / GMU property? Can expect that there >>> might be several SoCs having the same GPU, but different perfmode_bw >>> entry? >> >> I presume this is SoC specific ? But today the XXX_build_bw_table() are >> already SoC specific, so where should this go ? > > XXX_build_bw_table() are GPU-specific. There are cases of several SoCs > sharing the same GPU on them. So it's gpu-specific > >> Downstream specifies this in the adreno-gpulist.h, which is the equivalent >> here. >