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Wed, 08 Jan 2025 12:10:22 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 508CALNh003045 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Jan 2025 12:10:21 GMT Received: from [10.219.57.57] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 8 Jan 2025 04:10:18 -0800 Message-ID: Date: Wed, 8 Jan 2025 17:40:09 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu To: Konrad Dybcio , CC: , , , , , , References: <20241227110024.30203-1-quic_pbrahma@quicinc.com> <1c8af731-c551-4d72-84a0-f14d57bec4ec@oss.qualcomm.com> Content-Language: en-US From: Pratyush Brahma In-Reply-To: <1c8af731-c551-4d72-84a0-f14d57bec4ec@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: YoQtExhHSDPmSlFymms8lJD3RJu8-Ahl X-Proofpoint-ORIG-GUID: YoQtExhHSDPmSlFymms8lJD3RJu8-Ahl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 priorityscore=1501 mlxscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 mlxlogscore=856 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501080099 On 12/30/2024 6:49 PM, Konrad Dybcio wrote: > On 27.12.2024 12:00 PM, Pratyush Brahma wrote: >> Add the device node for gfx smmu that is required for gpu >> specific address translations. >> >> This patch depends on the patch series [1] posted by Imran Shaik >> adding the clock support for gpu. >> >> [1] https://lore.kernel.org/all/802d32f1-ff7e-4d61-83f1-f804ee1750ed@oss.qualcomm.com/ >> >> Signed-off-by: Pratyush Brahma >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 37 +++++++++++++++++++++++++++ >> 1 file changed, 37 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> index 80226992a65d..8eb688e2df0a 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -816,6 +816,43 @@ >> #power-domain-cells = <1>; >> }; >> >> + adreno_smmu: iommu@3da0000 { >> + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", >> + "qcom,smmu-500", "arm,mmu-500"; >> + reg = <0x0 0x3da0000 0x0 0x20000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <2>; >> + dma-coherent; >> + >> + power-domains = <&gpucc GPU_CC_CX_GDSC>; >> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >> + <&gpucc GPU_CC_AHB_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >> + <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >> + <&gpucc GPU_CC_HUB_AON_CLK>; >> + clock-names = "gcc_gpu_memnoc_gfx_clk", >> + "gcc_gpu_snoc_dvm_gfx_clk", >> + "gpu_cc_ahb_clk", >> + "gpu_cc_hlos1_vote_gpu_smmu_clk", >> + "gpu_cc_cx_gmu_clk", >> + "gpu_cc_hub_cx_int_clk", >> + "gpu_cc_hub_aon_clk"; > Most of these entries look totally bogus, please make sure you only > reference the ones actually required These entries are exactly similar to the ones we use in sa8775p as well [1] and the usecases haven't changed between qcs8300 and sa8775p. Can you please let me know which entries you find irrelevant here? [1] commit 1a1ff00c1626c "arm64: dts: qcom: sa8775p: add the GPU IOMMU node" > > Konrad -- Thanks and Regards Pratyush Brahma