From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stanimir Varbanov Subject: Re: [PATCH 1/3] clk: qcom: gdsc: Add support for gdscs with HW control Date: Tue, 25 Oct 2016 16:01:07 +0300 Message-ID: References: <1477304297-5248-1-git-send-email-sricharan@codeaurora.org> <1477304297-5248-2-git-send-email-sricharan@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wm0-f52.google.com ([74.125.82.52]:37745 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753785AbcJYNBM (ORCPT ); Tue, 25 Oct 2016 09:01:12 -0400 Received: by mail-wm0-f52.google.com with SMTP id c78so23193935wme.0 for ; Tue, 25 Oct 2016 06:01:12 -0700 (PDT) In-Reply-To: <1477304297-5248-2-git-send-email-sricharan@codeaurora.org> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: Sricharan R , sboyd@codeaurora.org, mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, rnayak@codeaurora.org, stanimir.varbanov@linaro.org Hi Sricharan, On 10/24/2016 01:18 PM, Sricharan R wrote: > From: Rajendra Nayak > > Some GDSCs might support a HW control mode, where in the power > domain (gdsc) is brought in and out of low power state (while > unsued) without any SW assistance, saving power. > Such GDSCs can be configured in a HW control mode when powered on > until they are explicitly requested to be powered off by software. > > Signed-off-by: Rajendra Nayak > Signed-off-by: Sricharan R > --- > drivers/clk/qcom/gdsc.c | 15 +++++++++++++++ > drivers/clk/qcom/gdsc.h | 1 + > 2 files changed, 16 insertions(+) > > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index f12d7b2..a5e1c8c 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -55,6 +55,13 @@ static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg) > return !!(val & PWR_ON_MASK); > } > > +static int gdsc_hwctrl(struct gdsc *sc, bool en) > +{ > + u32 val = en ? HW_CONTROL_MASK : 0; > + > + return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val); > +} > + > static int gdsc_toggle_logic(struct gdsc *sc, bool en) > { > int ret; > @@ -164,6 +171,10 @@ static int gdsc_enable(struct generic_pm_domain *domain) > */ > udelay(1); > > + /* Turn on HW trigger mode if supported */ > + if (sc->flags & HW_CTRL) > + gdsc_hwctrl(sc, true); Could you check gdsc_hwctrl() for an error. -- regards, Stan