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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6ecf8f3dsm108180966b.110.2025.04.25.03.09.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Apr 2025 03:09:58 -0700 (PDT) Message-ID: Date: Fri, 25 Apr 2025 12:09:56 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP To: Wenbin Yao , catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: krishna.chundru@oss.qualcomm.com, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_cang@quicinc.com, quic_qianyu@quicinc.com References: <20250425092955.4099677-1-quic_wenbyao@quicinc.com> <20250425092955.4099677-4-quic_wenbyao@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250425092955.4099677-4-quic_wenbyao@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDA3MyBTYWx0ZWRfX2OhREWt6b6OM T0aKX5brQ2Lj9P2PM0kro5KshQpki2JBLLXutc2A9p4wEAlSJllVAJIrPJxLtjUikq34JlTy3A6 25gWlJssVtxxtRlIZOiEAgzff1w+wVZ019tkQn3IC8oU4osAX3Fe6MzktWrmLvSplZRySD/pIMp 6p8Qr6+vX/isUvwFlnhBG+jpf+XVz7KjFk+HM7xWmPpXvwiml8Bo7pg+juSz9Maw8REhIlbak6S JxM5lQVIyMIwR7nfuMmXl7IrbiC8IhACrj9EcjFTfbPQ0D8Di+nFaoz8NX9ZqenO6Ea+kEgt9Sy r3Vw7lg+sfqKAy/b320JIhynjoIbvtvH+wkUKQTx/vVwh4dFsskmYpwStSlwmd5NO8v/Utasf8V GiCAVyXyKgvcEbovxcoYQZyNx2wNU33iZGhqN47qFiEG1AKBsfDgj+eSQ4x/y5FJUQZf438T X-Authority-Analysis: v=2.4 cv=bs1MBFai c=1 sm=1 tr=0 ts=680b5f78 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=VUPiE-F7cVA44BgGhqEA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 13qUtqbmvramfmDujohIFJ9v3IGos99Y X-Proofpoint-GUID: 13qUtqbmvramfmDujohIFJ9v3IGos99Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=990 mlxscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250073 On 4/25/25 11:29 AM, Wenbin Yao wrote: > From: Qiang Yu > > Add perst, wake and clkreq sideband signals and required regulators in > PCIe3 controller and PHY device tree node. Describe the voltage rails of > the x8 PCI slots for PCIe3 port. > > Signed-off-by: Qiang Yu > Signed-off-by: Wenbin Yao > --- > arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 118 ++++++++++++++++++++++ > 1 file changed, 118 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts > index 470c4f826..88dfd2199 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts > +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts > @@ -318,6 +318,48 @@ vreg_wcn_3p3: regulator-wcn-3p3 { > regulator-boot-on; > }; > > + vreg_pcie_12v: regulator-pcie-12v { > + compatible = "regulator-fixed"; > + > + regulator-name = "VREG_PCIE_12V"; > + regulator-min-microvolt = <12000000>; > + regulator-max-microvolt = <12000000>; > + > + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie_x8_12v>; Please keep the property-n property-names order throughout the patch with that: Reviewed-by: Konrad Dybcio Konrad