From: Shawn Lin <shawn.lin@rock-chips.com>
To: palash.kambar@oss.qualcomm.com, mani@kernel.org,
James.Bottomley@HansenPartnership.com,
martin.petersen@oracle.com
Cc: shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org,
linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org,
bvanassche@acm.org, nitin.rawat@oss.qualcomm.com
Subject: Re: [PATCH v4 1/2] ufs: core: Configure only active lanes during link
Date: Mon, 20 Apr 2026 08:37:19 +0800 [thread overview]
Message-ID: <e97a27bf-9fe2-efe9-3732-3661d0818af6@rock-chips.com> (raw)
In-Reply-To: <20260417045602.3042928-2-palash.kambar@oss.qualcomm.com>
在 2026/04/17 星期五 12:56, palash.kambar@oss.qualcomm.com 写道:
> From: Palash Kambar <palash.kambar@oss.qualcomm.com>
>
> The number of connected lanes detected during UFS link startup can be
> fewer than the lanes specified in the device tree. The current driver
> logic attempts to configure all lanes defined in the device tree,
> regardless of their actual availability. This mismatch may cause
> failures during power mode changes.
>
> Hence, Add a check during link startup to ensure that only the lanes
> actually discovered are considered valid. If a mismatch is detected,
> fail the initialization early, preventing the driver from entering
> an unsupported configuration that could cause power mode transition
> failures.
>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Palash Kambar <palash.kambar@oss.qualcomm.com>
> ---
> drivers/ufs/core/ufshcd.c | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
> index 31950fc51a4c..10f8d2b552be 100644
> --- a/drivers/ufs/core/ufshcd.c
> +++ b/drivers/ufs/core/ufshcd.c
> @@ -5035,6 +5035,40 @@ void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
> }
> EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
>
> +static int ufshcd_validate_link_params(struct ufs_hba *hba)
> +{
> + int ret, val;
> +
> + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
> + &val);
> + if (ret)
> + goto out;
> +
> + if (val != hba->lanes_per_direction) {
> + dev_err(hba->dev, "Tx lane mismatch [config,reported] [%d,%d]\n",
> + hba->lanes_per_direction, val);
> + ret = -ENOLINK;
> + goto out;
> + }
> +
> + ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
> + &val);
> + if (ret)
> + goto out;
> +
> + if (val != hba->lanes_per_direction) {
> + dev_err(hba->dev, "Rx lane mismatch [config,reported] [%d,%d]\n",
> + hba->lanes_per_direction, val);
> + ret = -ENOLINK;
> + goto out;
> + }
> +
> +return 0;
> +
> +out:
> + return ret;
> +}
> +
> /**
> * ufshcd_link_startup - Initialize unipro link startup
> * @hba: per adapter instance
> @@ -5108,6 +5142,10 @@ static int ufshcd_link_startup(struct ufs_hba *hba)
> goto out;
> }
>
> + ret = ufshcd_validate_link_params(hba);
> + if (ret)
> + goto out;
> +
> /* Include any host controller configuration via UIC commands */
> ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
> if (ret)
next prev parent reply other threads:[~2026-04-20 0:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-17 4:56 [PATCH v4 0/2] Add post change sequence for link start notify palash.kambar
2026-04-17 4:56 ` [PATCH v4 1/2] ufs: core: Configure only active lanes during link palash.kambar
2026-04-17 16:32 ` Bart Van Assche
2026-04-20 0:37 ` Shawn Lin [this message]
2026-04-20 9:40 ` Manivannan Sadhasivam
2026-04-22 11:42 ` Palash Kambar
2026-04-17 4:56 ` [PATCH v4 2/2] ufs: ufs-qcom: Enable Auto Hibern8 clock request support palash.kambar
2026-04-20 9:40 ` Manivannan Sadhasivam
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