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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id r3-20020a2eb603000000b002a8c1462ecbsm2244685ljn.137.2023.05.10.21.56.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 May 2023 21:56:18 -0700 (PDT) Message-ID: Date: Thu, 11 May 2023 07:56:17 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v6 8/8] drm/msm/dpu: tear down DSC data path when DSC disabled Content-Language: en-GB To: Kuogee Hsieh , dri-devel@lists.freedesktop.org, robdclark@gmail.com, sean@poorly.run, swboyd@chromium.org, dianders@chromium.org, vkoul@kernel.org, daniel@ffwll.ch, airlied@gmail.com, agross@kernel.org, andersson@kernel.org Cc: quic_abhinavk@quicinc.com, quic_jesszhan@quicinc.com, quic_sbillaka@quicinc.com, marijn.suijten@somainline.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <1683756453-22050-1-git-send-email-quic_khsieh@quicinc.com> <1683756453-22050-9-git-send-email-quic_khsieh@quicinc.com> From: Dmitry Baryshkov In-Reply-To: <1683756453-22050-9-git-send-email-quic_khsieh@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 11/05/2023 01:07, Kuogee Hsieh wrote: > Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(), > dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions > to tear down DSC data path if DSC data path was setup previous. > > Signed-off-by: Kuogee Hsieh > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 44 +++++++++++++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 +++++ > 2 files changed, 51 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 94b805b..6500589 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -1214,6 +1214,45 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, > mutex_unlock(&dpu_enc->enc_lock); > } > > +static void dpu_encoder_dsc_pipe_clr(struct dpu_encoder_virt *dpu_enc, > + struct dpu_hw_dsc *hw_dsc, > + struct dpu_hw_pingpong *hw_pp) > +{ > + struct dpu_encoder_phys *cur_master = dpu_enc->cur_master; > + struct dpu_hw_ctl *ctl; > + > + ctl = cur_master->hw_ctl; > + > + if (hw_dsc->ops.dsc_disable) > + hw_dsc->ops.dsc_disable(hw_dsc); > + > + if (hw_pp->ops.disable_dsc) > + hw_pp->ops.disable_dsc(hw_pp); > + > + if (hw_dsc->ops.dsc_bind_pingpong_blk) > + hw_dsc->ops.dsc_bind_pingpong_blk(hw_dsc, PINGPONG_NONE); > + > + if (ctl->ops.update_pending_flush_dsc) > + ctl->ops.update_pending_flush_dsc(ctl, hw_dsc->idx); > +} > + > +static void dpu_encoder_unprep_dsc(struct dpu_encoder_virt *dpu_enc) > +{ > + /* coding only for 2LM, 2enc, 1 dsc config */ > + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; > + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; > + int i; > + > + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { > + hw_pp[i] = dpu_enc->hw_pp[i]; > + hw_dsc[i] = dpu_enc->hw_dsc[i]; > + > + if (hw_pp[i] && hw_dsc[i]) > + dpu_encoder_dsc_pipe_clr(dpu_enc, hw_dsc[i], hw_pp[i]); > + } > + > +} > + > static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, > struct drm_atomic_state *state) > { > @@ -2090,6 +2129,9 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) > phys_enc->hw_pp->merge_3d->idx); > } > > + if (dpu_enc->dsc) > + dpu_encoder_unprep_dsc(dpu_enc); > + > intf_cfg.stream_sel = 0; /* Don't care value for video mode */ > intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); > > @@ -2101,6 +2143,8 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) > if (phys_enc->hw_pp->merge_3d) > intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; > > + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); > + > if (ctl->ops.reset_intf_cfg) > ctl->ops.reset_intf_cfg(ctl, &intf_cfg); > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 832a6a7..b34dac5 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -577,6 +577,7 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, > u32 intf_active = 0; > u32 wb_active = 0; > u32 merge3d_active = 0; > + u32 dsc_active; > > /* > * This API resets each portion of the CTL path namely, > @@ -606,6 +607,12 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_ctl *ctx, > wb_active &= ~BIT(cfg->wb - WB_0); > DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); > } > + > + if (cfg->dsc) { > + dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); > + dsc_active &= ~cfg->dsc; > + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); > + } > } > > static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, -- With best wishes Dmitry