* [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes
@ 2025-07-11 11:14 Manikanta Mylavarapu
2025-07-30 11:43 ` Konrad Dybcio
0 siblings, 1 reply; 3+ messages in thread
From: Manikanta Mylavarapu @ 2025-07-11 11:14 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt, conor+dt, linux-arm-msm,
devicetree, linux-kernel
Cc: quic_srichara, quic_varada, kathiravan.thirumoorthy
Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
operates on serial engine 2, designated as i2c0, and on serial engine 3,
designated as i2c1. Add both the i2c0 and i2c1 nodes.
Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq5424.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index 66bd2261eb25..858b9c714a13 100644
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -425,6 +425,28 @@ uart1: serial@1a84000 {
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
};
+ i2c0: i2c@1a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x01a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
+ assigned-clock-rates = <64000000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@1a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x01a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&gcc GCC_QUPV3_I2C1_CLK>;
+ assigned-clock-rates = <64000000>;
+ status = "disabled";
+ };
+
spi0: spi@1a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x01a90000 0 0x4000>;
base-commit: 58ba80c4740212c29a1cf9b48f588e60a7612209
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes
2025-07-11 11:14 [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes Manikanta Mylavarapu
@ 2025-07-30 11:43 ` Konrad Dybcio
2025-08-11 7:20 ` Manikanta Mylavarapu
0 siblings, 1 reply; 3+ messages in thread
From: Konrad Dybcio @ 2025-07-30 11:43 UTC (permalink / raw)
To: Manikanta Mylavarapu, andersson, konradybcio, robh, krzk+dt,
conor+dt, linux-arm-msm, devicetree, linux-kernel
Cc: quic_srichara, quic_varada, kathiravan.thirumoorthy
On 7/11/25 1:14 PM, Manikanta Mylavarapu wrote:
> Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
> operates on serial engine 2, designated as i2c0, and on serial engine 3,
> designated as i2c1. Add both the i2c0 and i2c1 nodes.
>
> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq5424.dtsi | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> index 66bd2261eb25..858b9c714a13 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
> @@ -425,6 +425,28 @@ uart1: serial@1a84000 {
> interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + i2c0: i2c@1a88000 {
> + compatible = "qcom,geni-i2c";
> + reg = <0 0x01a88000 0 0x4000>;
> + clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
> + clock-names = "se";
> + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
> + assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
> + assigned-clock-rates = <64000000>;
This is very wrong, the in-driver handling should be enough.
If not, add an opp-table.
Konrad
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes
2025-07-30 11:43 ` Konrad Dybcio
@ 2025-08-11 7:20 ` Manikanta Mylavarapu
0 siblings, 0 replies; 3+ messages in thread
From: Manikanta Mylavarapu @ 2025-08-11 7:20 UTC (permalink / raw)
To: Konrad Dybcio, andersson, konradybcio, robh, krzk+dt, conor+dt,
linux-arm-msm, devicetree, linux-kernel
Cc: quic_srichara, quic_varada, kathiravan.thirumoorthy
On 7/30/2025 5:13 PM, Konrad Dybcio wrote:
> On 7/11/25 1:14 PM, Manikanta Mylavarapu wrote:
>> Serial engines 2 and 3 on the IPQ5424 support I2C. The I2C instance
>> operates on serial engine 2, designated as i2c0, and on serial engine 3,
>> designated as i2c1. Add both the i2c0 and i2c1 nodes.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/ipq5424.dtsi | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 66bd2261eb25..858b9c714a13 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -425,6 +425,28 @@ uart1: serial@1a84000 {
>> interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + i2c0: i2c@1a88000 {
>> + compatible = "qcom,geni-i2c";
>> + reg = <0 0x01a88000 0 0x4000>;
>> + clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
>> + clock-names = "se";
>> + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
>> + assigned-clocks = <&gcc GCC_QUPV3_I2C0_CLK>;
>> + assigned-clock-rates = <64000000>;
>
> This is very wrong, the in-driver handling should be enough.
> If not, add an opp-table.
>
Hi Konrad,
Thank you for your review and valuable feedback.
I will incorporate an opp-table entry with a 64MHz frequency and submit a revised patch.
Thanks & Regards,
Manikanta.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-07-11 11:14 [PATCH v1] arm64: dts: qcom: ipq5424: add i2c nodes Manikanta Mylavarapu
2025-07-30 11:43 ` Konrad Dybcio
2025-08-11 7:20 ` Manikanta Mylavarapu
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