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Tue, 22 Oct 2024 07:10:59 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49M7AvfS002562 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 07:10:57 GMT Received: from [10.217.216.152] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Oct 2024 00:10:53 -0700 Message-ID: Date: Tue, 22 Oct 2024 12:40:50 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/11] clk: qcom: add support for GCC on SAR2130P To: Dmitry Baryshkov , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Philipp Zabel , "Konrad Dybcio" CC: , , , , Kalpak Kawadkar References: <20241021-sar2130p-clocks-v2-0-383e5eb123a2@linaro.org> <20241021-sar2130p-clocks-v2-8-383e5eb123a2@linaro.org> Content-Language: en-US From: Taniya Das In-Reply-To: <20241021-sar2130p-clocks-v2-8-383e5eb123a2@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ne6XEp-d1zFEcTtnSyCMasdCf3VIvZeF X-Proofpoint-GUID: Ne6XEp-d1zFEcTtnSyCMasdCf3VIvZeF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 spamscore=0 mlxscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 mlxlogscore=796 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410220045 On 10/21/2024 4:00 PM, Dmitry Baryshkov wrote: > Add driver for the Global Clock Controller as present on the Qualcomm > SAR2130P platform. This is based on the msm-5.10 tree, tag > KERNEL.PLATFORM.1.0.r4-00400-NEO.0. > > Co-developed-by: Kalpak Kawadkar > Signed-off-by: Kalpak Kawadkar > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-sar2130p.c | 2326 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 2336 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index e5d7c89b0dab6b4fc7133d8e348ae61d38f91770..5f7bf9db76cfcef1ab18a6ba09fb4dc506695f9d 100644 > --- a/drivers/clk/qcom/Kconfig > + > +static struct gdsc pcie_0_gdsc = { > + .gdscr = 0x7b004, > + .collapse_ctrl = 0x62200, > + .collapse_mask = BIT(0), > + .pd = { > + .name = "pcie_0_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = VOTABLE | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc pcie_0_phy_gdsc = { > + .gdscr = 0x7c000, > + .collapse_ctrl = 0x62200, > + .collapse_mask = BIT(3), > + .pd = { > + .name = "pcie_0_phy_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = VOTABLE | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc pcie_1_gdsc = { > + .gdscr = 0x9d004, > + .collapse_ctrl = 0x62200, > + .collapse_mask = BIT(1), > + .pd = { > + .name = "pcie_1_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = VOTABLE | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc pcie_1_phy_gdsc = { > + .gdscr = 0x9e000, > + .collapse_ctrl = 0x62200, > + .collapse_mask = BIT(4), > + .pd = { > + .name = "pcie_1_phy_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = VOTABLE | RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc usb30_prim_gdsc = { > + .gdscr = 0x49004, > + .pd = { > + .name = "usb30_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = RETAIN_FF_ENABLE, > +}; > + > +static struct gdsc usb3_phy_gdsc = { > + .gdscr = 0x60018, > + .pd = { > + .name = "usb3_phy_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = RETAIN_FF_ENABLE, > +}; > + Dimtry, could you also add, "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc" static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc = { .gdscr = 0x8d204, .pd = { .name = "hlos1_vote_mm_snoc_mmu_tbu_hf0_gdsc", }, .pwrsts = PWRSTS_OFF_ON, .flags = VOTABLE, }; "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc" --> 0x8d054 "hlos1_vote_turing_mmu_tbu0_gdsc" --> 0x8d05c "hlos1_vote_turing_mmu_tbu1_gdsc" --> 0x8d060 -- Thanks & Regards, Taniya Das.