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Mon, 16 Feb 2026 00:14:45 -0800 (PST) X-Received: by 2002:a17:90b:28c4:b0:340:bca2:cf82 with SMTP id 98e67ed59e1d1-356a7a44588mr7342762a91.4.1771229685380; Mon, 16 Feb 2026 00:14:45 -0800 (PST) Received: from [10.218.41.33] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3567eba9b2esm15943085a91.9.2026.02.16.00.14.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Feb 2026 00:14:44 -0800 (PST) Message-ID: Date: Mon, 16 Feb 2026 13:44:40 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/1] arm64: dts: qcom: monaco-evk: Add Mezzanine To: Bjorn Andersson Cc: konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mohd.anwar@oss.qualcomm.com, krishna.chundru@oss.qualcomm.com, monish.chunara@oss.qualcomm.com References: <20260210103821.4169-1-umang.chheda@oss.qualcomm.com> <20260210103821.4169-2-umang.chheda@oss.qualcomm.com> Content-Language: en-US From: Umang Chheda In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE2MDA2OCBTYWx0ZWRfX8GV9nbwhKd/o s8WOeiJwV3Aj6RdQvFa6cXQMYlMm9r/d91V0Cgk2TCKfPE4Vefw6YNB2ElY5OM4HO1IUIgDTUTL /6mt1jmWmk+g5zK2CA7LqRuqmdqlYjGsEhOfq3hjwrBAkNbxk/YDeESJCdMdRUQd7IlGHe5bEiM hNfVYvl5eqTFRlh53eFPn4b30K0eK0bX1rRdHffmnFcW4a4yzlscCkq18l5G8spYVs40Or0+0rT qNaZFNVecjFklCHg2MGH9EA6CoZSjwYAYgMxw134hFkeBD+OxWH7apEcY6cKTyi9N7YVaRyDtWl NcXQZyTaXA3jDWH77LPjD5um4Mry4HBBhyonYLNrD+F9u9sd+KdoAgQNIL97YJgDFYdE5Qgresy EAHYZexWyFv5ygY4opWhOn2drs+GKyfSg+56hljOnccZeQK/Fh/dz2UXH2wq0Aanv8cNFFs2PI/ tCQice5ylValJAObwOw== X-Proofpoint-GUID: m3KT3Mq1uFH-hbpGYvsau515C4nEMyj- X-Proofpoint-ORIG-GUID: m3KT3Mq1uFH-hbpGYvsau515C4nEMyj- X-Authority-Analysis: v=2.4 cv=EbXFgfmC c=1 sm=1 tr=0 ts=6992d1f6 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=MCphP8ZxGBsxnHqrgG0A:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-16_03,2026-02-16_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602160068 Hello Bjorn, On 2/13/2026 1:33 AM, Bjorn Andersson wrote: > On Tue, Feb 10, 2026 at 04:08:21PM +0530, Umang Chheda wrote: >> diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-mezzanine.dtso > [..] >> +&i2c15 { >> + #address-cells = <1>; >> + #size-cells = <0>; > Do we need to repeat this? It's in the top-level i2c15 definition > already? Yes this is required to be repeated in case of DTSO -- else seeing DT binding error if these cells are not added here. Seems the compiler is not looking at what is present in the Base DT first and is considering the default values for address and size cells and throwing error. Had to add similarly add for PCIe node as well to suppress binding errors. > >> + >> + status = "okay"; > I presume this overlay is used on top of monaco-evk.dtb, which already > says that status is okay. Ack > > > That said, I don't see a "clock-frequency" in either node, so I presume > you have an error/warning in your kernel log about this. But unless you > have reason to change that in your overlay, I think that's a unrelated > patch on the monaco-evk.dts - which I would like you to send, separately. Ack, will share a separate patch to fix this issue. > >> + >> + eeprom1: eeprom@52 { >> + compatible = "giantec,gt24c256c", "atmel,24c256"; >> + reg = <0x52>; >> + pagesize = <64>; >> + >> + nvmem-layout { >> + compatible = "fixed-layout"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + }; >> + }; >> +}; >> + > [..] >> +&tlmm { >> + tc9563_resx_n: tc9563-resx-state { >> + pins = "gpio124"; >> + function = "gpio"; >> + >> + bias-disable; >> + input-disable; >> + output-enable; >> + power-source = <0>; > Does these properties really match the TLMM binding? Please double > check. Double checked on this -- all the properties match the TLMM bindings. > > Regards, > Bjorn > >> + }; >> +}; >> -- >> 2.34.1 Thanks, Umang